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is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 1 rev. 00d, 8/17/2010 1gb (x8, x16) ddr2 sdram features ? ? clock ? frequency ? up ? to ? 400mhz ? ? 8 ? internal ? banks ? for ? concurrent ? operation ? ? 4 \ bit ? prefetch ? architecture ? ? programmable ? cas ? latency: ? 3, ? 4, ? 5, ? 6 ? and ? 7 ? ? programmable ? additive ? latency: ? 0, ? 1, ? 2, ? 3, ? 4, ? 5 ? and ? 6 ? ? write ? latency ? = ? read ? latency \ 1 ? ? programmable ? burst ? sequence: ? sequential ? or ? interleave ? ? programmable ? burst ? length: ? 4 ? and ? 8 ? ? automatic ? and ? controlled ? precharge ? command ? ? power ? down ? mode ? ? auto ? refresh ? and ? self ? refresh ? ? refresh ? interval: ? 7.8 ? s ? (8192 ? cycles/64 ? ms) ? ? ocd ? (off \ chip ? driver ? impedance ? adjustment) ? ? odt ? (on \ die ? termination) ? ? weak ? strength ? data \ output ? driver ? option ? ? bidirectional ? differential ? data ? strobe ? (single \ ended ? data \ strobe ? is ? an ? optional ? feature) ? ? on \ chip ? dll ? aligns ? dq ? and ? dqs ? transitions ? with ? ck ? transitions ? ? dqs# ? can ? be ? disabled ? for ? single \ ended ? data ? strobe ? ? read ? data ? strobe ? supported ? (x8 ? only) ? ? differential ? clock ? inputs ? ck ? and ? ck# ? ? vdd ? and ? vddq ? = ? 1.8v ? ? 0.1v ? ? pasr ? (partial ? array ? self ? refresh) ? ? sstl_18 ? interface ? ? tras ? lockout ? supported ? ? operating ? temperature: ? commercial ? (t a ? = ? 0c ? to ? 70c ? ; ? t c ? = ? 0c ? to ? 85c) ? industrial ? (t a ? = ?\ 40c ? to ? 85c; ? t c ? = ?\ 40c ? to ? 95c) ? automotive, ? a1 ? (t a ? = ?\ 40c ? to ? 85c; ? t c ? = ?\ 40c ? to ? 95c) ? automotive, ? a2 ? (t a ? = ?\ 40c ? to ? 105c; ? t c ? = ?\ 40c ? to ? 105c) ? options ?? ? ? configuration: ? ? 128mx8 ? (16m ? x ? 8 ? x ? 8 ? banks) ? ? 64mx16 ? (8m ? x ? 16 ? x ? 8 ? banks) ?? ? package: ? ? 60 \ ball ? fbga ? for ? x8 ? ? 84 \ ball ? fbga ? for ? x16 ? ? address ? table ? parameter 128mx8 ? 64mx16 row ? addressing a0 \ a13 ? a0 \ a12 column ? addressing a0 \ a9 ? a0 \ a9 bank ? addressing ba0 \ ba2 ? ba0 \ ba2 precharge ? addressing a10 ? a10 clock ? cycle ? timing ? ? \ 37c ? \ 3d ? \ 25e ? \ 25d ? units ? speed ? grade ? ddr2 \ 533c ? ddr2 \ 667d ddr2 \ 800e ddr2 \ 800d ?? cl \ trcd \ trp ? 4 \ 4 \ 4 ? 5 \ 5 \ 5 6 \ 6 \ 6 5 \ 5 \ 5 tck ? tck ? (cl=3) ? 5 ? 5 5 5 ns ? tck ? (cl=4) ? 3.75 ? 3.75 3.75 3.75 ns ? tck ? (cl=5) ? 3.75 ? 3 3 2.5 ns ? tck ? (cl=6) ? 3.75 ? 3 2.5 2.5 ns ? tck ? (cl=7) ? 3.75 ? 3 2.5 2.5 ns ? frequency ? (max) ? 266 ? 333 400 400 mhz ? note: ? the ?\ 37c ? device ? specification ? is ? shown ? for ? reference ? only. ? preliminary ? information ? august ? 2010 ? copyright ? 2010 integrated silicon solution, inc. all rights rese rved. issi reserves the right to make changes to this specifi cation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, produc ts or services descri bed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fail ure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect it s safety or effectiveness. prod ucts are not authorized for use in such applications unless integrated silicon solution, inc. re ceives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon soluti on, inc is adequately protected under the circumstances
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 2 rev. 00d, 8/17/2010 package ? ball \ out ? and ? description ? ddr2 ? sdram ? (128mx8) ? bga ? ball \ out ? (top \ view) ? (8.00mm ? x ? 13.65mm ? body, ? 0.8mm ? pitch) ? description input ? clocks clock ? enable chip ? select command ? control ? pins address bank ? address i/o data ? strobe redundant ? data ? strobe input ? data ? mask supply ? voltage ground dq ? power ? supply dq ? ground reference ? voltage dll ? power ? supply dll ? ground on ? die ? termination ? enable no ? connect vddl vssdl nc vss vddq vssq vref odt ba[2:0] dq[7:0] dqs, ? dqs# rdqs, ? rdqs# dm vdd symbol ck, ? ck# cke cs# ras#,cas#,we# a[13:0] notes: 1. ? pins ? b3 ? and ? a2 ? have ? identical ? capacitance ? as ? pins ? b7 ? and ? a8. 2. ? for ? a ? read, ? when ? enabled, ? strobe ? pair ? rdqs ? & ? rdqs# ? are ? identical ? in ? function ? and ? timing ? to ? strobe ? pair ? dqs ? & ? dqs# ? and ? input ? masking ? function ? is ? disabled. 3. ? the ? function ? of ? dm ? or ? rdqs/rdqs# ? are ? enabled ? by ? emrs ? command. 4. ? vddl ? and ? vssdl ? are ? power ? and ? ground ? for ? the ? dll. ? it ? is ? recommended ? that ? they ? are ? isolated ? on ? the ? device ? from ? vdd, ? vddq, ? vss, ? and ? vssq.
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 3 rev. 00d, 8/17/2010 ddr2 ? sdram ? (64mx16) ? bga ? ball \ out ? (top \ view) ? (8.00mm ? x ? 13.65mm ? body, ? 0.8mm ? pitch) ? description input ? clocks clock ? enable chip ? select command ? control ? inputs address bank ? address i/o upper ? byte ? data ? strobe lower ? byte ? data ? strobe input ? data ? mask supply ? voltage ground dq ? power ? supply dq ? ground reference ? voltage dll ? power ? supply dll ? ground on ? die ? termination ? enable no ? connect symbol ck, ? ck# cke cs# dq[15:0] udqs, ? udqs# ldqs, ? ldqs# udm, ? ldm ras#,cas#,we# a[12:0] ba[2:0] vref vddl vssdl nc odt vdd vss vddq vssq note: vddl ? and ? vssdl ? are ? power ? and ? ground ? for ? the ? dll. ? it ? is ? recommended ? that ? they ? are ? isolated ? on ? the ? device ? from ? vdd, ? vddq, ? vss, ? and ? vssq. 1 2 345 6 789 a b c d e f g h j k l m n p r vdd dq14 vddq dq12 vdd dq6 vddq dq4 vddl ba2 vss vdd nc vssq dq9 vssq nc vssq dq1 vssq vref cke ba0 a10/ap a3 a7 a12 vss udm vddq dq11 vss ldm vddq dq3 vss we ba1 a1 a5 a9 nc vssq udqs vddq dq10 vssq ldqs vddq dq2 vssdl ras cas a2 a6 a11 nc udqs vssq dq8 vssq ldqs vssq dq0 vssq ck ck cs a0 a4 a8 nc vddq dq15 vddq dq13 vddq dq7 vddq dq5 vdd odt vdd vss not populated
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 4 rev. 00d, 8/17/2010 functional ? description ? power \ up ? and ? initialization ? ddr2 ? sdrams ? must ? be ? powered ? up ? and ? initialized ? in ? a ? predefined ? manner. ? operational ? procedures ? other ? than ? those ? specified ? may ? result ? in ? undefined ? operation. ?? power \ up ? and ? initialization ? sequence ? the ? following ? sequence ? is ? required ? for ? power \ up ? and ? initialization. ? 1. either ? one ? of ? the ? following ? sequence ? is ? required ? for ? power \ up: ? a. while ? applying ? power, ? attempt ? to ? maintain ? cke ? below ? 0.2 ? x ? vddq ? and ? odt 1 ? at ? a ? low ? state ? (all ? other ? inputs ? may ? be ? undefined.) ? the ? vdd ? voltage ? ramp ? time ? must ? be ? no ? greater ? than ? 200 ? ms ? from ? when ? vdd ? ramps ? from ? 300 ? mv ? to ? vdd(min); ? and ? during ? the ? vdd ? voltage ? ramp, ? |vdd \ vddq| ?? 0.3 ? v. ? once ? the ? ramping ? of ? the ? supply ? voltages ? is ? complete ? (when ? vddq ? crosses ? vddq(min)), ? the ? supply ? voltage ? specifications ? provided ? in ? the ? table ? recommended ? dc ? operating ? conditions ? (sstl_1.8) , ? prevail . ? ? vdd, ? vddl ? and ? vddq ? are ? driven ? from ? a ? single ? power ? converter ? output, ? and ? ? vtt ? is ? limited ? to ? 0.95v ? max, ? and ? ? vref ? tracks ? vddq/2, ? vref ? must ? be ? within ? ? 300mv ? with ? respect ? to ? vddq/2 ? during ? supply ? ramp ? time. ? ? vddq ?? vref ? must ? be ? met ? at ? all ? times ? b. while ? applying ? power, ? attempt ? to ? maintain ? cke ? below ? 0.2 ? x ? vddq ? and ? odt 1 ? at ? a ? low ? state ? (all ? other ? inputs ? may ? be ? undefined, ? voltage ? levels ? at ? i/os ? and ? outputs ? must ? be ? less ? than ? vddq ? during ? voltage ? ramp ? time ? to ? avoid ? dram ? latch \ up. ? during ? the ? ramping ? of ? the ? supply ? voltages, ? vdd ?? vddl ?? vddq ? must ? be ? maintained ? and ? is ? applicable ? to ? both ? ac ? and ? dc ? levels ? until ? the ? ramping ? of ? the ? supply ? voltages ? is ? complete, ? which ? is ? when ? vddq ? crosses ? vddq ? min. ? once ? the ? ramping ? of ? the ? supply ? voltages ? is ? complete, ? the ? supply ? voltage ? specifications ? provided ? in ? the ? table ? recommended ? dc ? operating ? conditions ? (sstl \ 1.8) , ? prevail. ? ? apply ? vdd/vddl ? before ? or ? at ? the ? same ? time ? as ? vddq. ? ? vdd/vddl ? voltage ? ramp ? time ? must ? be ? no ? greater ? 200 ? ms ? from ? when ? vdd ? ramps ? from ? 300 ? mv ? to ? vdd(min) ? . ? ? apply ? vddq ? before ? or ? at ? the ? same ? time ? as ? vtt. ? ? the ? vddq ? voltage ? ramp ? time ? from ? when ? vdd(min) ? is ? achieved ? on ? vdd ? to ? the ? vddq(min) ? is ? achieved ? on ? vddq ? must ? be ? no ? greater ? than ? 500 ? ms. ? 2. start ? clock ? and ? maintain ? stable ? condition. ? 3. for ? the ? minimum ? of ? 200 ? s ? after ? stable ? power ? (vdd, ? vddl, ? vddq, ? vref, ? and ? vtt ? values ? are ? in ? the ? range ? of ? the ? minimum ? and ? maximum ? values ? specified ? in ? the ? table ? recommended ? dc ? operating ? conditions ? (sstl \ 1.8)) ? and ? stable ? clock ? (ck, ? ck#), ? then ? apply ? nop ? or ? deselect ? and ? assert ? a ? logic ? high ? to ? cke. ? 4. wait ? minimum ? of ? 400 ? ns ? then ? issue ? a ? precharge ? all ? command. ? during ? the ? 400 ? ns ? period, ? a ? nop ? or ? deselect ? command ? must ? be ? issued ? to ? the ? dram. ? 5. issue ? an ? emrs ? command ? to ? emr(2). ? 6. issue ? an ? emrs ? command ? to ? emr(3). ? 7. issue ? emrs ? to ? enable ? dll. ? 8. issue ? a ? mode ? register ? set ? command ? for ? dll ? reset. ? 9. issue ? a ? precharge ? all ? command. ? 10. issue ? 2 ? or ? more ? auto \ refresh ? commands. ? 11. issue ? a ? mrs ? command ? with ? low ? to ? a8 ? to ? initialize ? device ? operation. ? (i.e. ? to ? program ? operating ? parameters ? without ? resetting ? the ? dll.) ? 12. wait ? at ? least ? 200 ? clock ? cycles ? after ? step ? 8 ? and ? then ? execute ? ocd ? calibration ? (off ? chip ? driver ? impedance ? adjustment). ? if ? ocd ? calibration ? is ? not ? used, ? emrs ? default ? command ? (a9=a8=a7=high) ? followed ? by ? emrs ? ocd ? calibration ? mode ? exit ? command ? (a9=a8=a7=low) ? must ? be ? issued ? with ? other ? operating ? parameters ? of ? emr(1). ? 13. the ? ddr2 ? sdram ? is ? now ? ready ? for ? normal ? operation. ? ? note: ? 1. to ? guarantee ? odt ? off, ? vref ? must ? be ? valid ? and ? a ? low ? level ? must ? be ? applied ? to ? the ? odt ? pin. ? ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 5 rev. 00d, 8/17/2010 initialization ? sequence ? after ? power \ up ? diagram ? tch tcl tis ck ck# odt ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ command nop pre all emrs mrs ref any com pre all ref mrs emrs emrs 400ns trp tmrd dll enable dll reset minimum 200 cycles ocd default ocd cal. mode exit ~ ~ ~ ~ tis ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ tmrd trp trfc trfc follow ocd flowchart tmrd toit programming ? the ? mode ? register ? and ? extended ? mode ? registers ? for ? application ? flexibility, ? burst ? length, ? burst ? type, ? cas# ? latency, ? dll ? reset ? function, ? write ? recovery ? time ? (wr) ? are ? user ? defined ? variables ? and ? must ? be ? programmed ? with ? a ? mode ? register ? set ? (mrs) ? command. ? additionally, ? dll ? disable ? function, ? driver ? impedance, ? additive ? cas ? latency, ? odt ? (on ? die ? termination), ? single \ ended ? strobe, ? and ? ocd ? (off ? chip ? driver ? impedance ? adjustment) ? are ? also ? user ? defined ? variables ? and ? must ? be ? programmed ? with ? an ? extended ? mode ? register ? set ? (emrs) ? command. ? contents ? of ? the ? mode ? register ? (mr) ? or ? extended ? mode ? registers ? emr[1] ? and ? emr[2] ? can ? be ? altered ? by ? re \ executing ? the ? mrs ? or ? emrs ? commands. ? even ? if ? the ? user ? chooses ? to ? modify ? only ? a ? subset ? of ? the ? mr, ? emr[1], ? or ? emr[2] ? variables, ? all ? variables ? within ? the ? addressed ? register ? must ? be ? redefined ? when ? the ? mrs ? or ? emrs ? commands ? are ? issued. ? the ? x16 ? option ? does ? not ? have ? a13, ? so ? all ? references ? to ? this ? address ? can ? be ? ignored ? for ? this ? option. ? ? mrs, ? emrs ? and ? reset ? dll ? do ? not ? affect ? memory ? array ? contents, ? which ? mean ? re \ initialization ? including ? those ? can ? be ? executed ? at ? any ? time ? after ? power \ up ? without ? affecting ? memory ? array ? contents. ? ddr2 ? mode ? register ? (mr) ? setting ?? the ? mode ? register ? stores ? the ? data ? for ? controlling ? the ? various ? operating ? modes ? of ? ddr2 ? sdram. ? it ? controls ? cas# ? latency, ? burst ? length, ? burst ? sequence, ? dll ? reset, ? twr ? and ? active ? power ? down ? exit ? time ? to ? make ? ddr2 ? sdram ? useful ? for ? various ? applications. ? the ? default ? value ? of ? the ? mode ? register ? is ? not ? defined, ? therefore ? the ? mode ? register ? must ? be ? written ? after ? power \ up ? for ? proper ? operation. ? the ? mode ? register ? is ? written ? by ? asserting ? low ? on ? cs#, ? ras#, ? cas#, ? we#, ? ba0, ? ba1, ? and ? ba2 ? while ? controlling ? the ? state ? of ? address ? pins ? a0 ?\? a13. ? the ? ddr2 ? sdram ? should ? be ? in ? all ? bank ? precharge ? with ? cke ? already ? high ? prior ? to ? writing ? into ? the ? mode ? register. ? the ? mode ? register ? set ? command ? cycle ? time ? (tmrd) ? is ? required ? to ? complete ? the ? write ? operation ? to ? the ? mode ? register. ? the ? mode ? register ? contents ? can ? be ? changed ? using ? the ? same ? command ? and ? clock ? cycle ? requirements ? during ? normal ? operation ? as ? long ? as ? all ? banks ? are ? in ? the ? precharge ? state. ? the ? mode ? register ? is ? divided ? into ? various ? fields ? depending ? on ? functionality. ? burst ? length ? is ? defined ? by ? a0 ?\? a2 ? with ? options ? of ? 4 ? and ? 8 ? bit ? burst ? lengths. ? the ? burst ? length ? decodes ? are ? compatible ? with ? ddr ? sdram. ? burst ? address ? sequence ? type ? is ? defined ? by ? a3; ? cas ? latency ? is ? defined ? by ? a4 ?\? a6. ? the ? ddr2 ? doesn?t ? support ? half ? clock ? latency ? mode. ? a7 ? is ? used ? for ? test ? mode. ? a8 ? is ? used ? for ? dll ? reset. ? a7 ? must ? be ? set ? to ? low ? for ? normal ? mrs ? operation. ? write ? recovery ? time ? twr ? is ? defined ? by ? a9 ?\? a11. ? refer ? to ? the ? table ? for ? specific ? codes. ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 6 rev. 00d, 8/17/2010 mode ? register ? (mr) ? diagram ? a12 0 ba2 0 1 ba1 0 ba0 0 a11 a10 a9 a13 (1) 0 000 001 010 011 100 101 110 111 a8 0a7 10 1 a6 a5 a4 000 001 010 011 100 101 110 111 a3 0 1 a2 a1 a0 bl 0104 0118 address ? field mode ? register a2 burst ? length a6 cas ? latency a7 tm a11 wr interleave a3 bt 5 6 7 a1 burst ? type sequential a0 cas ? latency reserved a5 reserved reserved a4 3 4 a10 6 yes reserved a8 dll dll ? reset mode no normal 7 a9 8 reserved a12 pd1 2 3 4 5 wr(cycles) (2) slow ? exit(use ? txards) active ? power ? down ? exit ? time fast ? exit ? (use ? txard) ? notes: ? 1. a13 ? is ? reserved ? for ? future ? use ? and ? must ? be ? set ? to ? 0 ? when ? programming ? the ? mr. ? 2. wr(write ? recovery ? for ? autoprecharge) ? min ? is ? determined ? by ? tck ? max ? and ? wr ? max ? is ? determined ? by ? tck ? min. ? wr ? in ? clock ? cycles ? is ? calculated ? by ? dividing ? twr ? (in ? ns) ? by ? tck ? (in ? ns) ? and ? rounding ? up ? a ? non \ integer ? value ? to ? the ? next ? integer ? (wr[cycles] ? = ? twr(ns)/tck(ns)). ? the ? mode ? register ? must ? be ? programmed ? to ? this ? value. ? this ? is ? also ? used ? with ? trp ? to ? determine ? tdal. ? ddr2 ? extended ? mode ? register ? 1 ? (emr[1]) ? setting ?? the ? extended ? mode ? register ? 1 ? stores ? the ? data ? for ? enabling ? or ? disabling ? the ? dll, ? output ? driver ? strength, ? odt ? value ? selection ? and ? additive ? latency. ? the ? default ? value ? of ? the ? extended ? mode ? register ? is ? not ? defined, ? therefore ? the ? extended ? mode ? register ? must ? be ? written ? after ? power \ up ? for ? proper ? operation. ? extended ? mode ? register ? 1 ? is ? written ? by ? asserting ? low ? on ? cs#, ? ras#, ? cas#, ? we#, ? ba1, ? and ? ba2, ? and ? high ? on ? ba0, ? and ? controlling ? pins ? a0 ? ? ? a13. ? the ? ddr2 ? sdram ? should ? be ? in ? all ? bank ? precharge ? with ? cke ? already ? high ? prior ? to ? writing ? into ? the ? extended ? mode ? register. ? the ? mode ? register ? set ? command ? cycle ? time ? (tmrd) ? must ? be ? satisfied ? to ? complete ? the ? write ? operation ? to ? the ? extended ? mode ? register. ? mode ? register ? contents ? can ? be ? changed ? using ? the ? same ? command ? and ? clock ? cycle ? requirements ? during ? normal ? operation ? as ? long ? as ? all ? banks ? are ? in ? the ? precharge ? state. ? a0 ? is ? used ? for ? dll ? enable ? or ? disable. ? a1 ? is ? used ? for ? enabling ? reduced ? strength ? data \ output ? driver. ? a3 ?\? a5 ? determines ? the ? additive ? latency, ? a2 ? and ? a6 ? are ? used ? for ? odt ? value ? selection, ? a7 ?\? a9 ? are ? used ? for ? ocd ? control, ? a10 ? is ? used ? for ? dqs# ? disable ? and ? a11 ? is ? used ? for ? rdqs ? enable. ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 7 rev. 00d, 8/17/2010 dll ? enable/disable ? the ? dll ? must ? be ? enabled ? for ? normal ? operation. ? dll ? enable ? is ? required ? during ? power ? up ? initialization, ? and ? upon ? returning ? to ? normal ? operation ? after ? having ? the ? dll ? disabled. ? the ? dll ? is ? automatically ? disabled ? when ? entering ? self ? refresh ? operation ? and ? is ? automatically ? re \ enabled ? upon ? exit ? of ? self ? refresh ? operation. ? any ? time ? the ? dll ? is ? enabled ? (and ? subsequently ? reset), ? 200 ? clock ? cycles ? must ? occur ? before ? a ? read ? command ? can ? be ? issued ? to ? allow ? time ? for ? the ? internal ? clock ? to ? be ? synchronized ? with ? the ? external ? clock. ? failing ? to ? wait ? for ? synchronization ? to ? occur ? may ? result ? in ? a ? violation ? of ? the ? tac ? or ? tdqsck ? parameters. ? extended ? mode ? register ? 1(emr[1]) ? diagram ? a12 0 ba2 0 1 ba1 0 ba0 1 a11 (2) a13 (1) 0 0 rdqs/dm rdqs# dqs dqs# 100dmhi \ zdqsdqs# a10 0 1 dm hi \ zdqshi \ z 0 1 0 rdqs rdqs# dqs dqs# 111rdqshi \ zdqshi \ z a9 a8 a7 000 001 010 100 111 a5 a4 a3 000 a6a2 001 00 010 01 011 10 100 11 101 110 111 a1 a0 00 11 address ? field mode ? register dll ? enable a0 dll normal ? strength ? (100%) enable reduced ? strength ? (60%) disable a2 rtt reserved a1 d.i.c output ? drive ? impedance ? control 450 ? ohms a3 5 reserved rtt(nominal) a5 additive ? latency 1odt ? disabled 275 ? ohms a4 3 150 ? ohms a7 ocd ? calibration ? default (4) a6 rtt additive ? latency 0 a10 dqs# ocd ? calibration ? program a9 ocd ? program ocd ? calibration ? mode ? exit; ? maintain ? setting drive(1) a8 drive(0) adjust ? mode (3) a11 rdqs enable disable a12 qoff enable dqs# ouput ? buffer ? disabled rdqs ? enable a11 ? (rdqs) a10 ? (dqs#) strobe ? function ? matrix disable qof f output ? buffer ? enabled notes: ? 1. a13 ? is ? reserved ? for ? future ? use ? and ? must ? be ? set ? to ? 0 ? when ? programming ? the ? emr[1]. ? 2. if ? rdqs ? is ? enabled, ? the ? dm ? function ? is ? disabled. ? rdqs ? is ? active ? for ? reads ? and ? don?t ? care ? for ? writes. ? the ? x16 ? option ? does ? not ? support ? rdqs. ? this ? must ? be ? set ? to ? 0 ? when ? programming ? the ? emr[1] ? for ? the ? x16 ? option. ? 3. when ? adjust ? mode ? is ? issued, ? al ? from ? previously ? set ? value ? must ? be ? applied. ? 4. after ? setting ? to ? default, ? ocd ? calibration ? mode ? needs ? to ? be ? exited ? by ? setting ? a9 \ a7 ? to ? 000. ? ddr2 ? extended ? mode ? register ? 2 ? (emr[2]) ? setting ? the ? extended ? mode ? register ? 2 ? controls ? refresh ? related ? features. ? the ? default ? value ? of ? the ? extended ? mode ? register ? 2 ? is ? not ? defined. ? therefore, ? the ? extended ? mode ? register ? must ? be ? programmed ? during ? initialization ? for ? proper ? operation. ? the ? extended ? mode ? register ? 2 ? is ? written ? by ? asserting ? low ? on ? cs, ? ras, ? cas, ? we, ? ba0, ? ba2, ? and ? high ? on ? ba1, ? while ? controlling ? pins ? a0 \ a13. ? the ? ddr2 ? sdram ? should ? be ? in ? all ? bank ? precharge ? state ? with ? cke ? already ? high ? prior ? to ? writing ? into ? extended ? mode ? register ? 2. ? the ? mode ? register ? set ? command ? cycle ? time ? (tmrd) ? must ? be ? satisfied ? to ? complete ? the ? write ? operation ? to ? the ? extended ? mode ? register ? 2. ? mode ? register ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 8 rev. 00d, 8/17/2010 contents ? can ? be ? changed ? using ? the ? same ? command ? and ? clock ? cycle ? requirements ? during ? normal ? operation ? as ? long ? as ? all ? banks ? are ? in ? precharge ? state. ? extended ? mode ? register ? 2 ? (emr[2]) ? diagram ?? address field mode register ba2 0 ba1 1 ba0 0 a13 (1) 0 a7 0 1 a2 a1 a0 ba[2:0] 0 0 0 all combinations 0 0 1 000, 001, 010, 011 0 1 0 000, 001 0 1 1 000 1 0 0 010, 011, 100, 101, 110, 111 1 0 1 100, 101, 110, 111 1 1 0 110, 111 1 1 1 111 a2 pasr (3) quarter array 1/8 array a1 3/4 array half array a0 quarter array 1/8 array a4 (1) 0 partial array self refresh for 8 banks a3 (1) 0 full array half array a6 (1) 0 a5 (1) 0 a8 (1) 0 high temperature self-refresh rate enable a7 srft disable enable (2) a10 (1) 0 a9 (1) 0 a12 (1) 0 a11 (1) 0 ? notes: ? 1. a3 \ a6, ? and ? a8 \ a13 ? are ? reserved ? for ? future ? use ? and ? must ? be ? set ? to ? 0 ? when ? programming ? the ? emr[2]. ? 2. only ? industrial ? and ? automotive ? grade ? devices ? support ? the ? high ? temperature ? self \ refresh ? mode. ? the ? controller ? can ? set ? the ? emr ? (2) ? [a7] ? bit ? to ? enable ? this ? self \ refresh ? rate ? if ? tc ? > ? 85 c ? while ? in ? self \ refresh ? operation. ? toper ? may ? not ? be ? violated. ? 3. if ? pasr ? (partial ? array ? self ? refresh) ? is ? enabled, ? data ? located ? in ? areas ? of ? the ? array ? beyond ? the ? specified ? address ? range ? will ? be ? lost ? if ? self ? refresh ? is ? entered. ? data ? integrity ? will ? be ? maintained ? if ? tref ? conditions ? are ? met ? and ? no ? self ? refresh ? command ? is ? issued. ? ddr2 ? extended ? mode ? register ? 3 ? (emr[3]) ? setting ? no ? function ? is ? defined ? in ? extended ? mode ? register ? 3. ? the ? default ? value ? of ? the ? extended ? mode register ? 3 ? is ? not ? defined. ? therefore, ? the ? extended ? mode ? register ? 3 ? must ? be ? programmed ? during ? initialization ? for ? proper ? operation. ? ddr2 ? extended ? mode ? register ? 3 ? (emr[3]) ? diagram ? ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0* 1 1 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* address field mode register note: ? all ? bits ? in ? emr[3] ? except ? ba0 ? and ? ba1 ? are ? reserved ? for ? future ? use ? and ? must ? be ? set ? to ? 0 ? when ? programming ? the ? emr[3]. ??
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 9 rev. 00d, 8/17/2010 truth ? tables ? operation ? or ? timing ? that ? is ? not ? specified ? is ? illegal, ? and ? after ? such ? an ? event, ? in ? order ? to ? guarantee ? proper ? operation, ? the ? dram ? must ? be ? powered ? down ? and ? then ? restarted ? through ? the ? specified ? initialization ? sequence ? before ? normal ? operation ? can ? continue. ? command ? truth ? table ? previous ? cycle current ? cycle (extended) ? mode ? register h h llll ba 1, ? 2 refresh ? (ref) h h lll hx xxx1 self ? refresh ? entry h l lll hx xxx1, ? 8 h xxx l hhh single ? bank ? precharge hh l lhl ba xlx1, ? 2 precharge ? all ? banks hh l lh l xxhx1 bank ? activate hh l lhh ba 1, ? 2 write hh l hl l ba x lcolumn1, ? 2, ? 3, ? 10 write ? with ? auto ? precharge hh l hl lba x hcolumn1, ? 2, ? 3, ? 10 read hh l hlh ba x lcolumn1, ? 2, ? 3, ? 10 read ? with ? auto ? precharge hh l hlh ba x hcolumn1, ? 2, ? 3, ? 10 no ? operation ? (nop) h xl hhh xxxx 1 device ? deselect h xh xxx xxxx 1 h xxx l hhh h xxx l hhh function cke cs# ras# cas# we# ba2 \ ba0 an (9) \ a11 a10 a9 \ a0 notes opcode sel ? refresh ? exit l h x x x x 1, ? 7, ? 8 row ? address power ? down ? entry h l x x x x 1,4 power ? down ? exit l h x x x x 1, ? 4 ? notes: ? 1. all ? ddr2 ? sdram ? commands ? are ? defined ? by ? states ? of ? cs#, ? ras#, ? cas#, ? we# ? and ? cke ? at ? the ? rising ? edge ? of ? the ? clock. ? 2. bank ? addresses ? ba0, ? ba1, ? and ? ba2 ? (ba) ? determine ? which ? bank ? is ? to ? be ? operated ? upon. ? for ? (e)mrs ? ba ? selects ? an ? (extended) ? mode ? register. ? 3. burst ? reads ? or ? writes ? at ? bl=4 ? cannot ? be ? terminated ? or ? interrupted. ? see ? sections ? "reads ? interrupted ? by ? a ? read" ? and ? "writes ? interrupted ? by ? a ? write" ? for ? details. ? 4. the ? power ? down ? mode ? does ? not ? perform ? any ? refresh ? operations. ? the ? duration ? of ? power ? down ? is ? therefore ? limited ? by ? the ? refresh ? requirements ? 5. the ? state ? of ? odt ? does ? not ? affect ? the ? states ? described ? in ? this ? table. ? the ? odt ? function ? is ? not ? available ? during ? self ? refresh. ?? 6. ?x? ? means ? ?h ? or ? l ? (but ? a ? defined ? logic ? level)? ? 7. self ? refresh ? exit ? is ? asynchronous. ? 8. vref ? must ? be ? maintained ? during ? self ? refresh ? operation. ? 9. an ? refers ? to ? the ? msbs ? of ? addresseses. ? an=a13 ? for ? x8, ? and ? an=a12 ? for ? x16. ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 10 rev. 00d, 8/17/2010 clock ? enable ? (cke) ? truth ? table ? previous ? cycle (1) (n \ 1) current ? cycle (1) (n) l l x maintain ? power \ down 11, ? 13, ? 15 lhdeselect ? or ? nop power ? down ? exit 4, ? 8, ? 11, ? 13 l l x maintain ? self \ refresh 11, ? 15, ? 16 lhdeselect ? or ? nop self \ refresh ? exit 4, ? 5, ? 9, ? 16 bank(s) ? active h l deselect ? or ? nop active ? power ? down ? entry 4, ? 8, ? 10, ? 11, ? 13 hldeselect ? or ? nop precharge ? power ? down ? entry 4, ? 8, ? 10, ? 11, ? 13 h l refresh self \ refresh ? entry 6, ? 9, ? 11, ? 13 hh 7 refer ? to ? the ? command ? truth ? table notes power ? down self ? refresh all ? banks ? idle current ? state (2) cke command ? (n) (3) ras#, ? cas#, ? we#, ? cs# action ? (n) (3) notes: ? 1. cke ? (n) ? is ? the ? logic ? state ? of ? cke ? at ? clock ? edge ? n; ? cke ? (n?1) ? was ? the ? state ? of ? cke ? at ? the ? previous ? clock ? edge. ? 2. current ? state ? is ? the ? state ? of ? the ? ddr2 ? sdram ? immediately ? prior ? to ? clock ? edge ? n. ? 3. command ? (n) ? is ? the ? command ? registered ? at ? clock ? edge ? n, ? and ? action ? (n) ? is ? a ? result ? of ? command ? (n). ? 4. all ? states ? and ? sequences ? not ? shown ? are ? illegal ? or ? reserved ? unless ? explicitly ? described ? elsewhere ? in ? this ? document. ? 5. on ? self ? refresh ? exit, ? deselect ? or ? nop ? commands ? must ? be ? issued ? on ? every ? clock ? edge ? occurring ? during ? the ? txsnr ? period. ? read ? commands ? may ? be ? issued ? only ? after ? txsrd ? (200 ? clocks) ? is ? satisfied. ? 6. self ? refresh ? mode ? can ? only ? be ? entered ? from ? the ? all ? banks ? idle ? state. ? 7. must ? be ? a ? legal ? command ? as ? defined ? in ? the ? command ? truth ? table. ? 8. valid ? commands ? for ? power ? down ? entry ? and ? exit ? are ? nop ? and ? deselect ? only. ? 9. valid ? commands ? for ? self ? refresh ? exit ? are ? nop ? and ? deselect ? only. ? 10. power ? down ? and ? self ? refresh ? cannot ? be ? entered ? while ? read ? or ? write ? operations, ? (extended) ? mode ? register ? set ? operations ? or ? precharge ? operations ? are ? in ? progress. ? 11. tckemin ? of ? 3 ? clocks ? means ? cke ? must ? be ? registered ? on ? three ? consecutive ? positive ? clock ? edges. ? cke ? must ? remain ? at ? the ? valid ? input ? level ? the ? entire ? time ? it ? takes ? to ? achieve ? the ? 3 ? clocks ? of ? registration. ? thus, ? after ? any ? cke ? transition, ? cke ? may ? not ? transition ? from ? its ? valid ? level ? during ? the ? time ? period ? of ? tis ? + ? 2 ? x ? tck ? + ? tih. ? 12. the ? state ? of ? odt ? does ? not ? affect ? the ? states ? described ? in ? this ? table. ? the ? odt ? function ? is ? not ? available ? during ? self ? refresh. ? 13. the ? power ? down ? does ? not ? perform ? any ? refresh ? operations. ? the ? duration ? of ? power ? down ? mode ? is ? therefore ? limited ? by ? the ? refresh ? requirements ? outlined ? in ? this ? datasheet. ? 14. cke ? must ? be ? maintained ? high ? while ? the ? ddrii ? sdram ? is ? in ? ocd ? calibration ? mode. ? 15. ?x? ? means ? ?don?t ? care ? (including ? floating ? around ? vref)? ? in ? self ? refresh ? and ? power ? down. ? however ? odt ? must ? be ? driven ? high ? or ? low ? in ? power ? down ? if ? the ? odt ? function ? is ? enabled ? (bit ? a2 ? or ? a6 ? set ? to ? ?1? ? in ? emr[1] ? ). ? 16. vref ? must ? be ? maintained ? during ? self ? refresh ? operation. ? data ? mask ? (dm) ? truth ? table ? name ? (functional) dm dqs note write ? enable l valid 1 write ? inhibit h x1 note: ?? 1. used ? to ? mask ? write ? data, ? provided ? coincident ? with ? the ? corresponding ? data. ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 11 rev. 00d, 8/17/2010 commands ? deselect ? the ? deselect ? function ? (cs# ? high) ? prevents ? new ? commands ? from ? being ? executed ? by ? the ? ddr2 ? sdram. ? the ? ddr2 ? sdram ? is ? effectively ? deselected. ? operations ? already ? in ? progress ? are ? not ? affected. ? deselect ? is ? also ? referred ? to ? as ? command ? inhibit. ? no ? operation ? (nop) ? the ? no ? operation ? (nop) ? command ? is ? used ? to ? instruct ? the ? selected ? ddr2 ? sdram ? to ? perform ? a ? nop ? (cs# ? is ? low; ? ras#, ? cas#, ? and ? we# ? are ? high). ? this ? prevents ? unwanted ? commands ? from ? being ? registered ? during ? idle ? or ? wait ? states. ? operations ? already ? in ? progress ? are ? not ? affected. ? load ? mode ? (lm) ? the ? mode ? registers ? are ? loaded ? via ? bank ? address ? and ? address ? inputs. ? the ? bank ? address ? balls ? determine ? which ? mode ? register ? will ? be ? programmed. ? see ? ?mode ? register ? (mr)? ? in ? the ? next ? section. ? the ? lm ? command ? can ? only ? be ? issued ? when ? all ? banks ? are ? idle, ? and ? a ? subsequent ? executable ? command ? cannot ? be ? issued ? until ? tmrd ? is ? met. ? activate ? the ? activate ? command ? is ? used ? to ? open ? (or ? activate) ? a ? row ? in ? a ? particular ? bank ? for ? a ? subsequent ? access. ? the ? value ? on ? the ? bank ? address ? inputs ? determines ? the ? bank, ? and ? the ? address ? inputs ? select ? the ? row. ? this ? row ? will ? remains ? active ? (or ? open) ? for ? accesses ? until ? a ? precharge ? command ? is ? issued ? to ? that ? bank. ? a ? precharge ? command ? must ? be ? issued ? before ? opening ? a ? different ? row ? in ? the ? same ? bank. ? read ? the ? read ? command ? is ? used ? to ? initiate ? a ? burst ? read ? access ? to ? an ? active ? row. ? the ? value ? on ? the ? bank ? address ? inputs ? determine ? the ? bank, ? and ? the ? address ? provided ? on ? address ? inputs ? a0?a9 ? selects ? the ? starting ? column ? location. ? the ? value ? on ? input ? a10 ? determines ? whether ? or ? not ? auto ? precharge ? is ? used. ? if ? auto ? precharge ? is ? selected, ? the ? row ? being ? accessed ? will ? be ? precharged ? at ? the ? end ? of ? the ? read ? burst; ? if ? auto ? precharge ? is ? not ? selected, ? the ? row ? will ? remain ? open ? for ? subsequent ? accesses. ? ddr2 ? sdram ? also ? supports ? the ? al ? feature, ? which ? allows ? a ? read ? or ? write ? command ? to ? be ? issued ? prior ? to ? trcd(min) ? by ? delaying ? the ? actual ? registration ? of ? the ? read/write ? command ? to ? the ? internal ? device ? by ? al ? clock ? cycles. ? write ? the ? write ? command ? is ? used ? to ? initiate ? a ? burst ? write ? access ? to ? an ? active ? row. ? the ? value ? on ? the ? bank ? select ? inputs ? selects ? the ? bank, ? and ? the ? address ? provided ? on ? inputs ? a0?a9 ? selects ? the ? starting ? column ? location. ? the ? value ? on ? input ? a10 ? determines ? whether ? or ? not ? auto ? precharge ? is ? used. ? if ? auto ? precharge ? is ? selected, ? the ? row ? being ? accessed ? will ? be ? precharged ? at ? the ? end ? of ? the ? write ? burst; ? if ? auto ? precharge ? is ? not ? selected, ? the ? row ? will ? remain ? open ? for ? subsequent ? accesses. ? ddr2 ? sdram ? also ? supports ? the ? al ? feature, ? which ? allows ? a ? read ? or ? write ? command ? to ? be ? issued ? prior ? to ? trcd(min) ? by ? delaying ? the ? actual ? registration ? of ? the ? read/write ? command ? to ? the ? internal ? device ? by ? al ? clock ? cycles. ? input ? data ? appearing ? on ? the ? dq ? is ? written ? to ? the ? memory ? array ? subject ? to ? the ? dm ? input ? logic ? level ? appearing ? coincident ? with ? the ? data. ? if ? a ? given ? dm ? signal ? is ? registered ? low, ? the ? corresponding ? data ? will ? be ? written ? to ? memory; ? if ? the ? dm ? signal ? is ? registered ? high, ? the ? corresponding ? data ? inputs ? will ? be ? ignored, ? and ? a ? write ? will ? not ? be ? executed ? to ? that ? byte/column ? location. ? precharge ? the ? precharge ? command ? is ? used ? to ? deactivate ? the ? open ? row ? in ? a ? particular ? bank ? or ? the ? open ? row ? in ? all ? banks. ? the ? bank(s) ? will ? be ? available ? for ? a ? subsequent ? row ? activation ? a ? specified ? time ? (trp) ? after ? the ? precharge ? command ? is ? issued, ? except ? in ? the ? case ? of ? concurrent ? auto ? precharge, ? where ? a ? read ? or ? write ? command ? to ? a ? different ? bank ? is ? allowed ? as ? long ? as ? it ? does ? not ? interrupt ? the ? data ? transfer ? in ? the ? current ? bank ? and ? does ? not ? violate ? any ? other ? timing ? parameters. ? after ? a ? bank ? has ? been ? precharged, ? it ? is ? in ? the ? idle ? state ? and ? must ? be ? activated ? prior ? to ? any ? read ? or ? write ? commands ? being ? issued ? to ? that ? bank. ? a ? precharge ? command ? is ? allowed ? if ? there ? is ? no ? open ? row ? in ? that ? bank ? (idle ? state) ? or ? if ? the ? previously ? open ? row ? is ? already ? in ? the ? process ? of ? precharging. ? however, ? the ? precharge ? period ? will ? be ? determined ? by ? the ? last ? precharge ? command ? issued ? to ? the ? bank. ? refresh ? refresh ? is ? used ? during ? normal ? operation ? of ? the ? ddr2 ? sdram ? and ? is ? analogous ? to ? cas# \ before \ ras# ? (cbr) ? refresh. ? all ? banks ? must ? be ? in ? the ? idle ? mode ? prior ? to ? issuing ? a ? refresh ? command. ? this ? command ? is ? nonpersistent, ? so ? it ? must ? be ? issued ? each ? time ? a ? refresh ? is ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 12 rev. 00d, 8/17/2010 required. ? the ? addressing ? is ? generated ? by ? the ? internal ? refresh ? controller. ? this ? makes ? the ? address ? bits ? a ? ?don?t ? care? ? during ? a ? refresh ? command. ? self ? refresh ? the ? self ? refresh ? command ? can ? be ? used ? to ? retain ? data ? in ? the ? ddr2 ? sdram, ? even ? if ? the ? rest ? of ? the ? system ? is ? powered ? down. ? when ? in ? the ? self ? refresh ? mode, ? the ? ddr2 ? sdram ? retains ? data ? without ? external ? clocking. ? all ? power ? supply ? inputs ? (including ? vref) ? must ? be ? maintained ? at ? valid ? levels ? upon ? entry/exit ? and ? during ? self ? refresh ? operation. ? the ? self ? refresh ? command ? is ? initiated ? like ? a ? refresh ? command ? except ? cke ? is ? low. ? the ? dll ? is ? automatically ? disabled ? upon ? entering ? self ? refresh ? and ? is ? automatically ? enabled ? upon ? exiting ? self ? refresh. ? odt ? (on \ die ? termination) ? the ? on \ die ? termination ? feature ? allows ? the ? ddr2 ? sdram ? to ? easily ? implement ? an ? internal ? termination ? resistance ? (rtt). ? for ? the ? x8 ? option, ? odt ? can ? be ? configured ? for ? dq[7:0], ? dqs, ? dqs#, ? dm, ? rdqs, ? and ? rdqs# ? signals. ? for ? the ? x16 ? option, ? odt ? can ? be ? configured ? for ? dq[15:0], ? udqs, ? ldqs, ? udqs#, ? ldqs#, ? and ? udm, ? and ? ldm ? signals. ? the ? odt ? feature ? can ? be ? configured ? with ? the ? extended ? mode ? register ? set ? (emrs) ? command, ? and ? turned ? on ? or ? off ? using ? the ? odt ? input ? signal. ? before ? and ? after ? the ? emrs ? is ? issued, ? the ? odt ? input ? must ? be ? received ? with ? respect ? to ? the ? timings ? of ? taofd, ? tmod(max), ? taond; ? and ? the ? cke ? input ? must ? be ? held ? high ? throughout ? the ? duration ? of ? tmod(max). ? the ? ddr2 ? sdram ? supports ? the ? odt ? on ? and ? off ? functionality ? in ? active, ? standby, ? and ? power ? down ? modes, ? but ? not ? in ? self ? refresh ? mode. ? odt ? timing ? diagrams ? follow ? for ? active/standby ? mode ? and ? power ? down ? mode. ? emrs ? to ? odt ? update ? delay ? ck# command odt ck emrs nop nop nop nop nop old setting tmod(min) tmod(max) odt ready updated tis ~ ~ ~ taofd ~ ~ ~ taond odt ? timing ? for ? active/standby ? (idle) ? mode ? and ? standard ? active ? power \ down ? mode ? ck# cke odt ck rtt vih(ac) vil(ac) internal term. resistance tis tis taon(min) taon(max) taond taofd tis taof(min) taof(max) 012345 tis ~ ~ ~ ~ tanpd taxpd 67 notes: ? 1. both ? odt ? to ? power ? down ? entry ? and ? exit ? latency ? timing ? parameter ? tanpd ? and ? taxpd ? are ? met, ? therefore ? non \ power ? down ? mode ? timings ? have ? to ? be ? applied. ? 2. odt ? turn \ on ? time, ? taon(min) ? is ? when ? the ? device ? leaves ? high ? impedance ? and ? odt ? resistance ? begins ? to ? turn ? on. ? odt ? turn ? on ? time ? max, ? taon(max) ? is ? when ? the ? odt ? resistance ? is ? fully ? on. ? both ? are ? measured ? from ? taond. ? 3. odt ? turn ? off ? time ? min, ? taof(min), ? is ? when ? the ? device ? starts ? to ? turn ? off ? the ? odt ? resistance. ? odt ? turn ? off ? time ? max, ? taof(max) ? is ? when ? the ? bus ? is ? in ? high ? impedance. ? both ? are ? measured ? from ? taofd.
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 13 rev. 00d, 8/17/2010 odt ? timing ? for ? precharge ? power \ down ? mode ? note: ? both ? odt ? to ? power ? down ? endtry ? and ? exit ? latencies ? tanpd ? and ? taxpd ? are ? not ? met, ? therefore ? power \ down ? mode ? timings ? have ? to ? be ? applied.
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 14 rev. 00d, 8/17/2010 absolute ? maximum ? dc ? ratings ? symbol ? parameter ? rating ? units ? notes ? vdd ? voltage ? on ? vdd ? pin ? relative ? to ? vss ?\ 1.0 ? to ? 2.3 ? v ? 1, ? 3 ? vddq ? voltage ? on ? vddq ? pin ? relative ? to ? vss ?\? 0.5 ? to ? 2.3 ? v ? 1, ? 3 ? vddl ? voltage ? on ? vddl ? pin ? relative ? to ? vss ?\? 0.5 ? to ? 2.3 ? v ? 1, ? 3 ? vin, ? vout ? voltage ? on ? any ? pin ? relative ? to ? vss ?\? 0.5 ? to ? 2.3 ? v ? 1, ? 4 ? tstg ? storage ? temperature ?\ 55 ? to ? +150 ? c ? 1, ? 2 ? notes: ? 1. stresses ? greater ? than ? those ? listed ? under ? ?absolute ? maximum ? ratings? ? may ? cause ? permanent ? damage ? to ? the ? device. ? this ? is ? a ? stress ? rating ? only ? and ? functional ? operation ? of ? the ? device ? at ? these ? or ? any ? other ? conditions ? above ? those ? indicated ? in ? the ? operational ? sections ? of ? this ? specification ? is ? not ? implied. ? exposure ? to ? absolute ? maximum ? rating ? conditions ? for ? extended ? periods ? may ? affect ? reliability. ? 2. storage ? temperature ? is ? the ? case ? surface ? temperature ? on ? the ? center/top ? side ? of ? the ? dram. ? 3. vdd ? and ? vddq ? must ? be ? within ? 300mv ? of ? each ? other ? at ? all ? times; ? and ? vref ? must ? be ? not ? greater ? than ? 0.6 ? x ? vddq. ? when ? vdd ? and ? vddq ? and ? vddl ? are ? less ? than ? 500mv, ? vref ? may ? be ? equal ? to ? or ? less ? than ? 300mv. ? 4. voltage ? on ? any ? input ? or ? i/o ? may ? not ? exceed ? voltage ? on ? vddq. ? ? ac ? and ? dc ? operating ? conditions ? recommended ? dc ? operating ? conditions ? (sstl ?\? 1.8) ? symbol ?? parameter ? rating ? units ? ? notes ? min. ? ? typ. ? ? max. ? vdd ? supply ? voltage ? 1.7 ? 1.8 ? 1.9 ? v ? 1 ? vddl ? supply ? voltage ? for ? dll ? 1.7 ? 1.8 ? 1.9 ? v ? 5 ? vddq ? supply ? voltage ? for ? output ? 1.7 ? 1.8 ? 1.9 ? v ? 1, ? 5 ? vref ? input ? reference ? voltage ? 0.49*vddq ? 0.50*vddq ? 0.51*vddq ? mv ? 2, ? 3 ? vtt ? termination ? voltage ? vref \ 0.04 ? vref ? vref+0.04 ? v ? 3 ? notes: ? 1. there ? is ? no ? specific ? device ? vdd ? supply ? voltage ? requirement ? for ? sstl \ 1.8 ? compliance. ? however, ? under ? all ? conditions ? vddq ? must ? be ? less ? than ? or ? equal ? to ? vdd. ? 2. the ? value ? of ? vref ? may ? be ? selected ? by ? the ? user ? to ? provide ? optimum ? noise ? margin ? in ? the ? system. ? typically ? the ? value ? of ? vref ? is ? expected ? to ? be ? about ? 0.5 ? x ? vddq ? of ? the ? transmitting ? device ? and ? vref ? is ? expected ? to ? track ? variations ? in ? vddq. ? 3. peak ? to ? peak ? ac ? noise ? on ? vref ? may ? not ? exceed ? +/ \ 2% ? vref(dc). ? 4. vtt ? of ? transmitting ? device ? must ? track ? vref ? of ? receiving ? device. ? 5. ac ? parameters ? are ? measured ? with ? vdd, ? vddq ? and ? vddl ? tied ? together. ? ? operating ? temperature ? condition ? (1, ? 2, ? 3) ? symbol ? parameter ? rating ? units ? toper ? commercial ? operating ? temperature ? tc ? = ? 0 ? to ? 85, ? ta ? = ? 0 ? to ? 70 ? c ? toper ? industrial ? operating ? temperature, ? automotive ? operating ? temperature ? (a1) ? tc ? = ?\ 40 ? to ? 95, ? ta ? = ?\ 40 ? to ? 85 ? c ? toper ? automotive ? operating ? temperature ? (a2) ? tc ? = ?\ 40 ? to ? 105, ? ta ? = ?\ 40 ? to ? 105 ? c ? notes: ? 1. tc ? = ? operating ? case ? temperature ? at ? center ? of ? package. ? 2. ta ? = ? operating ? ambient ? temperature ? immediately ? above ? package ? center. ? 3. both ? temperature ? specifications ? must ? be ? met. ? thermal ? resistance ? package ? substrate ? theta \ ja ?? (airflow ? = ? 0m/s) ? theta \ ja ?? (airflow ? = ? 1m/s) ? theta \ ja ?? (airflow ? = ? 2m/s) ? theta \ jc ? units ? 60 \ ball ? 4 \ layer ? 35.8 ? 32.4 ? 29.2 ? 3 ? c/w ? 84 \ ball ? 4 \ layer ? 33.8 ? 30.4 ? 27.5 ? 3 ? c/w ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 15 rev. 00d, 8/17/2010 ac ? and ? dc ? logic ? input ? levels ? single \ ended ? dc ? input ? logic ? level ? symbol ? parameter ? min. ? ? max. ? units ? notes ? vih(dc) ?? dc ? input ? logic ? high ? vref ? + ? 0.125 ?? vddq ? + ? 0.3 ? v ? v ?? vil(dc) ?? dc ? input ? logic ? low ?\? 0.3 ? vref ?\? 0.125 ? v ?? single \ ended ? ac ? input ? logic ? level ? symbol ?? parameter ? ddr2 \ 533 ? ddr2 \ 667, ? 800 ? units ? min. ? ? max. ? min. ? ? max. ? vih(ac) ?? ac ? input ? logic ? high ? vref ? + ? 0.250 ? vddq ? + ? vpeak ? vref ? + ? 0.200 ? vddq ? + ? vpeak ? v ? vil(ac) ?? ac ? input ? logic ? low ? vssq ?\? vpeak ? vref ?\? 0.250 ? vssq ?\? vpeak ? vref ?\? 0.200 ? v ? ? note: ? refer ? to ? overshoot ? and ? undershoot ? specification ? for ? vpeak ? value: ? maximum ? peak ? amplitude ? allowed ? for ? overshoot ? and ? undershoot. ? ? ac ? input ? test ? conditions ? symbol ? condition ? value ? units ? notes ? vref ? input ? reference ? voltage ? 0.5 ? x ? vddq ? v ? 1 ? vref ? input ? signal ? maximum ? peak ? to ? peak ? swing ? 1.0 ? v ? 1 ? slew ? input ? signal ? minimum ? slew ? rate ? 1.0 ? v/ns ? 2, ? 3 ?? notes: ? 1. input ? waveform ? timing ? is ? referenced ? to ? the ? input ? signal ? crossing ? through ? the ? vih/il(ac) ? level ? applied ? to ? the ? device ? under ? test. ? 2. the ? input ? signal ? minimum ? slew ? rate ? is ? to ? be ? maintained ? over ? the ? range ? from ? vref ? to ? vih(ac) ? min ? for ? rising ? edges ? and ? the ? range ? from ? vref ? to ? vil(ac) ? max ? for ? falling ? edges ? as ? shown ? in ? the ? below ? figure. ? 3. ac ? timings ? are ? referenced ? with ? input ? waveforms ? switching ? from ? vil(ac) ? to ? vih(ac) ? on ? the ? positive ? transitions ? and ? vih(ac) ? to ? vil(ac) ? on ? the ? negative ? transitions. ? ac ? input ? test ? signal ? waveform ? v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss v swing(max) tr tf v ref - v il (ac) max tf falling slew = rising slew = v ih(ac) min - v ref tr differential ? input ? ac ? logic ? level ? symbol ? parameter ? ddr2 \ 533,667, ? 800 ? units ? notes ? min. ? max. ? vid(ac) ? ac ? differential ? input ? voltage ? 0.5 ? vddq ? v ? 1, ? 3 ? vix(ac) ? ac ? differential ? crosspoint ? voltage ? 0.5 ? x ? vddq \ 0.175 ? 0.5 ? x ? vddq+0.175 ? v ? 2 ? notes: ? 1. vid(ac) ? specifies ? the ? input ? differential ? voltage ? |vtr ?\ vcp ? | ? required ? for ? switching, ? where ? vtr ? is ? the ? true ? input ? signal ? (such ? as ? ck, ? dqs, ? ldqs ? or ? udqs) ? and ? vcp ? is ? the ? complementary ? input ? signal ? (such ? as ? ck#, ? dqs#, ? ldqs# ? or ? udqs#). ? the ? minimum ? value ? is ? equal ? to ? v ? ih(ac) ?\? v ? il(ac). ? 2. the ? typical ? value ? of ? vix(ac) ? is ? expected ? to ? be ? about ? 0.5 ? x ? vddq ? of ? the ? transmitting ? device ? and ? vix(ac) ? is ? expected ? to ? track ? variations ? in ? vddq. ? vix(ac) ? indicates ? the ? voltage ? at ? which ? differential ? input ? signals ? must ? cross. ? ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 16 rev. 00d, 8/17/2010 differential signal level waveform v ddq crossing point v ssq v tr v cp v id v ix or v ox differential ? ac ? output ? parameters ? symbol ? parameter ? min. ? ? max. ? units ? vox(ac) ?? ac ? differential ? crosspoint ? voltage ? 0.5 ? x ? vddq \ 0.125 ? 0.5 ? x ? vddq+0.125 ? v ? note: ? the ? typical ? value ? of ? vox(ac) ? is ? expected ? to ? be ? about ? 0.5 ? x ? vddq ? of ? the ? transmitting ? device ? and ? vox(ac) ? is ? expected ? to ? track ? variations ? in ? vddq. ? vox(ac) ? indicates ? the ? voltage ? at ? which ? differential ? output ? signals ? must ? cross. ? ? overshoot ? and ? undershoot ? specification ? ac ? overshoot ? and ? undershoot ? specification ? for ? address ? and ? control ? pins ? parameter ? ddr2 \ 533 ? ddr2 \ 667 ? ddr2 \ 800 ? unit ? maximum ? peak ? amplitude ? allowed ? for ? overshoot ? area ? 0.5 ? 0.5 ? 0.5 ? v ? maximum ? peak ? amplitude ? allowed ? for ? undershoot ? area ? 0.5 ? 0.5 ? 0.5 ? v ? maximum ? overshoot ? area ? above ? vdd * ? 0.8 ? 0.8 ? 0.66 ? v \ ns ? maximum ? undershoot ? area ? below ? vss * ? 0.8 ? 0.8 ? 0.66 ? v \ ns ? note: ? please ? refer ? to ? ac ? overshoot ? and ? undershoot ? definition ? diagram . ? ac ? overshoot ? and ? undershoot ? specification ? for ? clock, ? data, ? strobe ? and ? mask ? pins ? parameter ? ddr2 \ 533 ? ddr2 \ 667 ? ddr2 \ 800 ? unit ? maximum ? peak ? amplitude ? allowed ? for ? overshoot ? area ? 0.5 ? 0.5 ? 0.5 ? v ? maximum ? peak ? amplitude ? allowed ? for ? undershoot ? area ? 0.5 ? 0.5 ? 0.5 ? v ? maximum ? overshoot ? area ? above ? vddq* ? 0.23 ? 0.23 ? 0.23 ? v \ ns ? maximum ? undershoot ? area ? below ? vssq* ? 0.23 ? 0.23 ? 0.23 ? v \ ns ? note: ? please ? refer ? to ? ac ? overshoot ? and ? undershoot ? definition ? diagram . ? ac ? overshoot ? and ? undershoot ? definition ? diagram ? overshoot area maximum amplitude v dd /v ddq undershoot area maximum amplitude v ss /v ssq volts (v) time (ns)
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 17 rev. 00d, 8/17/2010 output ? buffer ? characteristics ? output ? ac ? test ? conditions ? symbol ? parameter ? sstl_18 ? units ? votr ? output ? timing ? measurement ? reference ? level ? 0.5 ? x ? vddq ? v ? note: ? the ? vddq ? of ? the ? device ? under ? test ? is ? referenced. ? ? output ? dc ? current ? drive ? symbol ? parameter ? sstl_18 ? units ? notes ? ioh(dc) ? output ? minimum ? source ? dc ? current ? 13.4 ? ma ? 1, ? 3, ? 4 ? iol(dc) ? output ? minimum ? sink ? dc ? current ?\ 13.4 ? ma ? 2, ? 3, ? 4 ? notes: ? 1. vddq ? = ? 1.7 ? v; ? vout ? = ? 1420 ? mv. ? (vout ?\? vddq)/ioh ? must ? be ? less ? than ? 21 ?? for ? values ? of ? vout ? between ? vddq ? and ? vddq ?\? 280 ? mv. ? 2. vddq ? = ? 1.7 ? v; ? vout ? = ? 280 ? mv. ? vout/iol ? must ? be ? less ? than ? 21 ?? for ? values ? of ? vout ? between ? 0 ? v ? and ? 280 ? mv. ? 3. the ? dc ? value ? of ? vref ? applied ? to ? the ? receiving ? device ? is ? set ? to ? vtt ? 4. the ? values ? of ? ioh(dc) ? and ? iol(dc) ? are ? based ? on ? the ? conditions ? given ? in ? notes ? 1 ? and ? 2. ? they ? are ? used ? to ? test ? device ? drive ? current ? capability ? to ? ensure ? vih ? min ? plus ? a ? noise ? margin ? and ? vil ? max ? minus ? a ? noise ? margin ? are ? delivered ? to ? an ? sstl_18 ? receiver. ? the ? actual ? current ? values ? are ? derived ? by ? shifting ? the ? desired ? driver ? operating ? point ? (see ? section ? 3.3 ? of ? jesd8 \ 15a) ? along ? a ? 21 ?? load ? line ? to ? define ? a ? convenient ? driver ? current ? for ? measurement. ? ocd ? default ? characteristics ? description ? parameter ? min. ? nom. ? max. ? units ? notes ? output ? impedance ?? normal ? 18 ? ohms see ? full ? strength ? default ? driver ? characteristics ? ohms ? 1, ? 2 ? output ? impedance ? step ? size ? for ? ocd ? calibration ?? 0 ?? 1.5 ? ohms ? 6 ? pull \ up ? and ? pull \ down ? mismatch ?? 0 ?? 4 ? ohms ? 1, ? 2, ? 3 ? output ? slew ? rate ? sout ? 1.5 ?? 5 ? v/ns ? 1, ? 4, ? 5, ? 7, ? 8, ? 9 ? notes: ? 1. absolute ? specifications ? (toper; ? vdd ? = ? +1.8v ? 0.1v, ? vddq ? = ? +1.8v ? 0.1v). ? dram ? i/o ? specifications ? for ? timing, ? voltage, ? and ? slew ? rate ? are ? no ? longer ? applicable ? if ? ocd ? is ? changed ? from ? default ? settings. ? 2. impedance ? measurement ? condition ? for ? output ? source ? dc ? current: ? vddq ? = ? 1.7 ? v; ? vout ? = ? 1420 ? mv; ? (voutvddq)/ioh ? must ? be ? less ? than ? 23.4 ?? for ? values ? of ? vout ? between ? vddq ? and ? vddq ?\? 280 ? mv. ? impedance ? measurement ? condition ? for ? output ? sink ? dc ? current: ? vddq ? = ? 1.7 ? v; ? vout ? = ? 280 ? mv; ? vout/iol ? must ? be ? less ? than ? 23.4 ?? for ? values ? of ? vout ? between ? 0 ? v ? and ? 280 ? mv. ? 3. mismatch ? is ? absolute ? value ? between ? pull \ up ? and ? pull \ down, ? both ? are ? measured ? at ? same ? temperature ? and ? voltage. ? 4. slew ? rate ? measured ? from ? vil(ac) ? to ? vih(ac). ? 5. the ? absolute ? value ? of ? the ? slew ? rate ? as ? measured ? from ? dc ? to ? dc ? is ? equal ? to ? or ? greater ? than ? the ? slew ? rate ? as ? measured ? from ? ac ? to ? ac. ? this ? is ? guaranteed ? by ? design ? and ? characterization. ? 6. this ? represents ? the ? step ? size ? when ? the ? ocd ? is ? near ? 18 ?? at ? nominal ? conditions ? across ? all ? process ? corners/variations ? and ? represents ? only ? the ? dram ? uncertainty. ? a ? 0 ?? value ? (no ? calibration) ? can ? only ? be ? achieved ? if ? the ? ocd ? impedance ? is ? 18 ?? +/ \ 0.75 ?? under ? nominal ? conditions. ? 7. dram ? output ? slew ? rate ? specification ? applies ? to ? 667 ? mt/s ? speed ? bins. ? 8. timing ? skew ? due ? to ? dram ? output ? slew ? rate ? mis \ match ? between ? dqs ? / ? dqs# ? and ? associated ? dq?s ? is ? included ? in ? tdqsq ? and ? tqhs ? specification. ? ? output ? capacitance ? paramater ? symbol ? \ 37c ? (ddr2 \ 533c) ? \ 3d ? (ddr2 \ 667d) ? \ 25e ? (ddr2 \ 800e)/ \ 25d ? (ddr2 \ 800d) ? units ? min ? max ? min ? max ? min ? max ? input ? capacitance ? (ck ? and ? ck#) ? cck ? 1.00 ? 2.00 ? 1.00 ? 2.00 ? 1.00 ? 2.00 ? pf ? input ? capacitance ? delta ? (ck ? and ? ck#) ? cdck ?? 0.25 ?? 0.25 ?? 0.25 ? pf ? input ? capacitance ? (all ? other ? input \ only ? pins) ? ci ? 1.00 ? 2.00 ? 1.00 ? 2.00 ? 1.00 ? 1.75 ? pf ? input ? capacitance ? delta ? (all ? other ? input \ only ? pins) ? cdi ?? 0.25 ?? 0.25 ?? 0.25 ? pf ? i/o ? capacitance ? (dq, ? dm, ? dqs, ? dqs#) ? cio ? 2.50 ? 4.00 ? 2.50 ? 3.50 ? 2.50 ? 3.50 ? pf ? i/o ? capacitance ? delta ? (dq, ? dm, ? dqs, ? dqs#) ? cdio ?? 0.50 ?? 0.50 ?? 0.50 ? pf ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 18 rev. 00d, 8/17/2010 odt ? dc ? electrical ? characteristics ? parameter/condition ? symbol ? min. ? nom. ? ? max. ? units ? ? notes ? rtt ? effective ? impedance ? value ? for ? emrs(a6=0, ? a2=1); ? 75 ? ohm ? rtt1(eff) ? 60 ? 75 ? 90 ? ohms ? 1 ? rtt ? effective ? impedance ? value ? for ? emrs(a6=1, ? a2=0); ? 150 ? ohm ? rtt2(eff) ? 120 ? 150 ? 180 ? ohms ? 1 ? rtt ? effective ? impedance ? value ? for ? emrs(a6=a2=1); ? 50 ? ohm ? rtt3(eff) ? 40 ? 50 ? 60 ? ohms ? 1 ? deviation ? of ? vm ? with ? respect ? to ? vddq/2 ? delta ? vm ?\ 6 ??? +6 ? % ? 2 ? note: ? 1. measurement ? definition ? for ? rtt(eff): ? apply ? vihac ? and ? vilac ? to ? test ? pin ? seperately, ? then ? measure ? current ? i(vihac) ? and ? i(vilac) ? respectively ? ? )) ac ( vil ( i )) ac ( vih ( i ) ac ( vil ) ac ( vih ) eff ( rtt ? ? = ? ? 2. measurement ? defintion ? for ? vm: ? measure ? voltage ? (vm) ? at ? test ? pin ? (midpoint) ? with ? no ? load: ? ? % 100 x 1 vddq vm ? x ? 2 vm ? ? ? ? ? ? ? = odt ? ac ? electrical ? characteristics ? and ? operating ? conditions ? symbol ? parameter/condition ? min. ? ? max. ? units ? notes ? taond ? odt ? turn \ on ? delay ? 2 ? 2 ? tck ?? taon ? odt ? turn \ on ? tac(min) ? tac(max)+0.7ns ? ns ? 1 ? taonpd ? odt ? turn \ on ? (power \ down ? mode) ? tac(min)+2 ? ns ? 2tck+tac(max)+1ns ? ns ? 3 ? taofd ? odt ? turn \ off ? delay ? 2.5 ? 2.5 ? tck ?? taof ? odt ? turn \ off ? tac(min) ? tac(max)+0.6ns ? ns ? 2 ? taofpd ? odt ? turn \ off ? (power \ down ? mode) ? tac(min)+2ns ? 2.5tck+tac+1ns ? ns ? 3 ? tanpd ? odt ? to ? power \ down ? mode ? entry ? l:atency ? 3 ?? tck ? 4 ? taxpd ? odt ? power ? down ? exit ? latency ? 8 ?? tck ? 4 ? notes: ? 1. odt ? turn ? on ? time ? min ? is ? when ? the ? de ? vice ? leaves ? high ? impedance ? and ? odt ? resistance ? begins ? to ? turn ? on. ? odt ? turn ? on ? time ? max ? is ? when ? the ? odt ? resistance ? is ? fully ? on. ? both ? are ? measured ? from ? t ? aond. ? 2. odt ? turn ? off ? time ? min ? is ? when ? the ? device ? starts ? to ? turn \ off ? odt ? resistance. ? odt ? turn ? off ? time ? max ? is ? when ? the ? bus ? is ? in ? high ? impedance. ? both ? are ? measured ? from ? taofd. ? 3. for ? standard ? active ? power \ down ? (with ? mr ? s ? a12 ? = ? ?0?), ? the ? non ? power ?\ down ? timings ? (taond, ? taon, ? taofd ? and ? taof) ? apply. ? 4. tanpd ? an ? d ? taxpd ? define ? the ? timing ? limit ? when ? either ? power ? down ? mode ? timings ? (taonpd, ? taofpd) ? or ? non \ power ? down ? mode ? timings ? ( ? taond, ? taofd) ? have ? to ? be ? applied ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 19 rev. 00d, 8/17/2010 idd specifications and conditions idd ? measurement ? conditions ? symbol ? parameter/condition ? idd0 ? operating ? current ?\? one ? bank ? active ?\? precharge: ? tck = tck(idd), trc = trc(idd), tras = trasmin(idd); cke is high, cs# is high between valid commands; address bus inputs are sw itching; data bus inputs are switching. idd1 ? operating ? current ?\? one ? bank ? active ?\? read ?\? precharge: ? iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), trc = trc(idd), tras = trasmin(idd), trcd = trcd(idd); cke is high, c s# is high between valid commands; address bus inputs are switching; data pattern is same as idd4w idd2p ? precharge ? power \ down ? current: ? ? all banks idle; tck = tck(idd); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating idd2q ? precharge ? standby ? current: ?? all banks idle; tck = tck(idd); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating idd2n ? precharge ? quiet ? standby ? current: ?? all banks idle; tck = tck(idd); cke is high, cs# is high; other control and address bus inputs are switching; data bus inputs a re switching idd3pf ? active ? power \ down ? current: ?? all banks open; tck = tck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating . ? mrs ? a12 ? bit ? is ? set ? to ? ?0?(fast ? power \ down ? exit). idd3ps ? active ? power \ down ? current: ?? all banks open; tck = tck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating . ? mrs ? a12 ? bit ? is ? set ? to ? ?1?(slow ? power \ down ? exit). ? idd3n ? active ? standby ? current: ?? all banks open; tck = tck(idd), tras = trasmax(idd), trp = trp( idd); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. idd4r ? operating ? current ?\? burst ? read: ? all banks open, continuous burst reads, iout = 0 ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), tras = trasmax(idd), trp = t rp(idd); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as idd4w idd4w ? operating ? current ?\? burst ? write: ?? all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching. ? idd5b ? burst ? auto \ refresh ? current: ?? tck = tck(idd); refresh command at every trfc(idd) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. idd5d ? distributed ? refresh ? current: ?? tck = tck(idd); refresh command frequency satisfying trefi; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. idd6 ? self \ refresh ? current: ?? ck and ck# at 0 v; cke 0.2 v; other control and address bus inputs are floating; data bus inputs are floating . idd7 ? operating ? bank ? interleave ? read ? current: ? 1. all ? bank ? interleaving ? reads, ? iout ? = ? 0ma; ? bl ? = ? 4, ? cl ? = ? cl(idd), ? al ? = ? trcd(idd) ?\? 1 ? x ? tck(idd); ? tck ? = ? tck(idd), ? trc ? = ? trc(idd), ? trrd ? = ? trrd(idd), ? tfaw ? = ? tfaw(idd), ? trcd ? = ? 1 ? x ? tck(idd); ? cke ? is ? high, ? cs ? is ? high ? between ? valid ? commands; ? address ? bus ? inputs ? are ? stable ? during ? deselects; ? data ? pattern ? is ? same ? as ? idd4r; ? notes: ? 1. data ? bus ? consists ? of ? dq, ? dm, ? dqs, ? dqs#, ? rdqs, ? rdqs#, ? ldqs, ? ldqs#, ? udqs, ? and ? udqs#. ? idd ? values ? must ? be ? met ? with ? all ? combinations ? of ? emrs ? bits ? 10 ? and ? 11. ? 2. for ? ddr2 \ 667/800 ? testing, ? tck ? in ? the ? conditions ? should ? be ? interpreted ? as ? tck(avg). ? 3. definitions ? for ? idd: ? a. low ? is ? defined ? as ? vin ?? vilac(max). ? b. high ? is ? defined ? as ? vin ?? vihac(min). ? c. stable ? = ? inputs ? stable ? at ? a ? high ? or ? low ? level. ? d. floating ? = ? inputs ? at ? vref ? = ? vddq/2. ? e. switching ? = ? inputs ? changing ? between ? high ? and ? low ? every ? other ? clock ? cycle ? (once ? per ? two ? clocks) ? for ? address ? and ? control ? signals, ? and ? inputs ? changing ? between ? high ? and ? low ? every ? other ? data ? transfer ? (once ? per ? clock) ? for ? dq ? signals ? not ? including ? masks ? or ? strobes. ? 4. legend: ? a=activate, ? ra=read ? with ? auto \ precharge, ? d=deselect. ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 20 rev. 00d, 8/17/2010 ? idd ? specifications ? symbol ? configuration ? \ 37c ? ddr2 \ 533c ? \ 3d ? ddr2 \ 667d ? \ 25e/25d ? ddr2 \ 800e/800d ? units ? idd0 ? x8 ? 80 ? 90 ? 100 ? ma ? x16 ? 110 ? 120 ? 130 ? ma ? idd1 ? x8 ? 95 ? 105 ? 115 ? ma ? x16 ? 130 ? 140 ? 150 ? ma ? idd2p ? x8/x16 ? 15 ? 15 ? 15 ? ma ? idd2n ? x8/x16 ? 40 ? 45 ? 50 ? ma ? idd2q ? x8 ? 40 ? 45 ? 50 ? ma ? x16 ? 45 ? 50 ? 55 ? ma ? idd3pf ? x8/x16 ? 30 ? 33 ? 38 ? ma ? idd3ps ? x8/x16 ? 18 ? 18 ? 18 ? ma ? idd3n ? x8/x16 ? 68 ? 72 ? 75 ? ma ? idd4r ? x8 ? 190 ? 210 ? 240 ? ma ? x16 ? 220 ? 260 ? 290 ? ma ? idd4w ? x8 ? 200 ? 220 ? 250 ? ma ? x16 ? 220 ? 260 ? 290 ? ma ? idd5b ? x8/x16 ? 250 ? 260 ? 270 ? ma ? idd5d ? x8/x16 ? 45 ? 45 ? 45 ? ma ? idd6 ? x8/x16 ? 8 ? 8 ? 8 ? ma ? idd7 ? x8 ? 270 ? 300 ? 310 ? ma ? x16 ? 310 ? 350 ? 360 ? ma ? notes: ? 1. idd ? specifications ? are ? tested ? after ? the ? device ? is ? properly ? initialized. ? 2. input ? slew ? rate ? is ? specified ? by ? ac ? parametric ? test ? condition. ? 3. idd ? parameters ? are ? specified ? with ? odt ? disabled. ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 21 rev. 00d, 8/17/2010 ac ? characteristics ? (ac ? operating ? conditions ? unless ? otherwise ? noted) ? parameter ? symbol ? \ 37c ? \ 3d ? \ 25e ? \ 25d ? units ? notes ? ddr2 \ 533c ? ddr2 \ 667d ? ddr2 \ 800e ? ddr2 \ 800d ? min ? max ? min ? max ? min ? max ? min ? max ? row ? cycle ? time ? trc ? 60 ?? 60 ?? 60 ?? 57.5 ?? ns ?? auto ? refresh ? row ? cycle ? time ? trfc ? 127.5 ?? 127.5 ? 127.5 ? 127.5 ? ns ? 11 ? row ? active ? time ? tras ? 45 ? 70k ? 45 ? 70k ? 45 ? 70k ? 45 ? 70k ? ns ? 21 ? row ? active ? to ? column ? address ? delay ? trcd ? 15 ?? 15 ?? 15 ?? 12.5 ?? ns ? 20 ? row ? active ? to ? row ? active ? delay ? trrd(x8) ? 7.5 ?? 7.5 ?? 7.5 ?? 7.5 ?? ns ?? trrd(x16) ? 10 ?? 10 ?? 10 ?? 10 ?? ns ?? four ? activate ? window ? tfaw(x8) ? 37.5 ?? 37.5 ?? 35 ?? 35 ?? ns ?? tfaw(x16) ? 50 ?? 50 ?? 45 ?? 45 ?? ns ?? column ? address ? to ? column ? address ? delay ? tccd ? 2 ?? 2 ?? 2 ?? 2 ?? tck ?? row ? precharge ? time ? trp ? 15 ?? 15 ?? 15 ?? 12.5 ?? ns ?? write ? recovery ? time ? twr ? 15 ?? 15 ?? 15 ?? 15 ?? ns ?? auto ? precharge ? write ? recovery ? + ? precharge ? time ? tdal ? min ? = ? twr+trp, ? max ? = ? n/a ? ns ? 12 ? clock ? cycle ? time ? tck3 ? (cl=3) ? 5 ? 8 ? 5 ? 8 ???? ? ns ? 2 ? tck4 ? (cl=4) ? 3.75 ? 8 ? 3.75 ? 8 ? 3.75 ? 8 ? 3.75 ? 8 ? ns ? 2 ? tck5 ? (cl=5) ?? ? 3 ? 8 ? 3 ? 8 ? 2.5 ? 8 ? ns ? 2 ? tck6 ? (cl=6) ????? 2.5 ? 8 ? 2.5 ? 8 ? ns ?? tck7 ? (cl=7) ???????? ? ns ?? clock ? high ? level ? width ? tch ? 0.45 ? 0.55 ? 0.48 ? 0.52 ? 0.48 ? 0.52 ? 0.48 ? 0.52 ? tck ?? clock ? low ? level ? width ? tcl ? 0.45 ? 0.55 ? 0.48 ? 0.52 ? 0.48 ? 0.52 ? 0.48 ? 0.52 ? tck ?? cycle ? to ? cycle ? tjitcc ? 250 ? 250 ? 200 ? 200 ? ps ?? data \ out ? edge ? to ? clock ? skew ? edge ? tac ?\ 0.5 ? 0.45 ?\ 0.45 ? 0.45 ?\ 0.4 ? 0.4 ?\ 0.4 ? 0.4 ? ns ?? dqs \ out ? edge ? to ? clock ? skew ? edge ? tdqsck ?\ 0.45 ? 0.4 ?\ 0.4 ? 0.4 ?\ 0.35 ? 0.35 ?\ 0.35 ? 0.35 ? ns ?? dqs \ out ? edge ? to ? clock ? skew ? edge ? tdqsq ?? 0.3 ?? 0.24 ?? 0.2 ?? 0.2 ? ns ?? data \ out ? hold ? time ? from ? dqs ? tqh ? min ? = ? thp(min) \ tqhs, ? max ? = ? n/a ? ns ?? data ? hold ? skew ? factor ? tqhs ?? 400 ?? 340 ?? 300 ?? 300 ? ps ?? clock ? half ? period ? thp ? min ? = ? tch(min)/tcl(min), ? max ? = ? n/a ? ns ? 5 ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 22 rev. 00d, 8/17/2010 ac ? characteristics ? (ac ? operating ? conditions ? unless ? otherwise ? noted) parameter ? symbol ? \ 37c ? \ 3d ? \ 25e ? \ 25d ? units ? notes ? ddr2 \ 533c ? ddr2 \ 667d ? ddr2 \ 800e ? ddr2 \ 800d ? min ? max ? min ? max ? min ? max ? min ? max ? input ? setup ? time ? (fast ? slew ? rate) ? tis ? 250 ?? 200 ?? 175 ?? 175 ?? ps ? 15,17 ? input ? hold ? time ? (fast ? slew ? rate) ? tih ? 375 ?? 275 ?? 250 ?? 250 ?? ps ? 15,17 ? input ? pulse ? width ? tipw ? 0.6 ?? 0.6 ?? 0.6 ?? 0.6 ?? tck ?? write ? dqs ? high ? level ? width ? tdqsh ? 0.35 ?? 0.35 ?? 0.35 ?? 0.35 ?? tck ?? write ? dqs ? low ? level ? width ? tdqsl ? 0.35 ?? 0.35 ?? 0.35 ?? 0.35 ?? tck ?? clk ? to ? first ? rising ? edge ? of ? dqs \ in ? tdqss ? min ? = ?\ 0.25tck, ? max ? = ? +0.25tck ? tck ?? data \ in ? setup ? time ? to ? dqs \ in ? (dq, ? dm) ? tds ? 100 ?? 100 ?? 50 ?? 50 ?? ps ? 16,17, 18 ? data \ in ? hold ? time ? to ? dqs \ in ? (dq, ? dm) ? tdh ? 225 ?? 175 ?? 125 ?? 125 ?? ps ? 16,17, 18 ? dqs ? falling ? edge ? from ? clk ? rising ? setup ? time ? tdss ? 0.2 ?? 0.2 ?? 0.2 ?? 0.2 ?? tck ?? dqs ? falling ? edge ? from ? clk ? rising ? hold ? time ? tdsh ? 0.2 ?? 0.2 ?? 0.2 ?? 0.2 ?? tck ?? dq ? & ? dm ? pulse ? width ? tdipw ? 0.35 ?? 0.35 ?? 0.35 ?? 0.35 ?? tck ?? read ? dqs ? preamble ? time ? trpre ? 0.9 ? 1.1 ? 0.9 ? 1.1 ? 0.9 ? 1.1 ? 0.9 ? 1.1 ? tck ?? read ? dqs ? postamble ? time ? trpst ? 0.4 ? 0.6 ? 0.4 ? 0.6 ? 0.4 ? 0.6 ? 0.4 ? 0.6 ? tck ?? write ? dqs ? preamble ? setup ? time ? twpres ? 0 ?? 0 ?? 0 ?? 0 ?? tck ?? write ? dqs ? preamble ? hold ? time ? twpreh ? 0.25 ?? 0.25 ?? 0.25 ?? 0.25 ?? tck ?? write ? dqs ? preamble ? time ? twpre ? 0.35 ?? 0.35 ?? 0.35 ?? 0.35 ?? tck ?? write ? dqs ? postamble ? time ? twpst ? 0.4 ? 0.6 ? 0.4 ? 0.6 ? 0.4 ? 0.6 ? 0.4 ? 0.6 ? tck ? 10 ? internal ? read ? to ? precharge ? command ? delay ? trtp ? 7.5 ?? 7.5 ?? 7.5 ?? 7.5 ?? ns ?? internal ? write ? to ? read ? command ? delay ? twtr ? 7.5 ?? 7.5 ?? 7.5 ?? 7.5 ?? ns ? 13 ? data \ out ? to ? high ? impedance ? from ? ck/ck# ? thz ? min ? = ? n/a, ? max ? = ? tac(max) ? ns ? 7 ? dqs/dqs# ? low ? impedance ? from ? ck/ck# ? tlz(dqs) ? min ? = ? tac(min), ? max ? = ? tac(max) ? ns ? 7 ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 23 rev. 00d, 8/17/2010 ac ? characteristics ? (ac ? operating ? conditions ? unless ? otherwise ? noted) parameter ? symbol ? \ 37c ? \ 3d ? \ 25e ? \ 25d ? units ? notes ? ddr2 \ 533c ? ddr2 \ 667d ? ddr2 \ 800e ? ddr2 \ 800d ? min ? max ? min ? max ? min ? max ? min ? max ? dq ? to ? low ? impedance ? from ? ck/ck# ? tlz(dq) ? min ? = ? 2 ? x ? tac(min), ? max ? = ? tac(max) ? ns ? 7 ? mode ? register ? set ? delay ? tmrd ? 2 ?? 2 ?? 2 ?? 2 ?? tck ? 9 ? ocd ? drive ? mode ? output ? delay ? tmod ? 0 ? 12 ? 0 ? 12 ? 0 ? 12 ? 0 ? 12 ? ns ?? odt ? drive ? mode ? output ? delay ? toit ? 0 ? 12 ? 0 ? 12 ? 0 ? 12 ? 0 ? 12 ? ns ?? exit ? self ? refresh ? to ? non \ read ? command ? txsnr ? min ? = ? t rfc ? + ? 10, ? max ?? = ? n/a ? ns ? 19 ? exit ? self ? refresh ? to ? read ? command ? txsrd ? 200 ?? 200 ?? 200 ?? 200 ?? t ck ?? exit ? precharge ? power ? down ? to ? any ? non \ read ? command ? txp ? 2 ?? 2 ?? 2 ?? 2 ?? t ck ? 14 ? exit ? active ? power ? down ? to ? read ? command ? txard ? 2 ?? 2 ?? 2 ?? 2 ?? t ck ?? exit ? active ? power ? down ? to ? read ? command ? (slow ? exit, ? low ? power) ? taxrds ? 6 \ al ?? 7 \ al ?? 8 \ al ?? 8 \ al ?? t ck ?? minimum ? time ? clocks ? remains ? on ? after ? cke ? asynchronously ? drops ? low ? tdelay ? min ? = ? t is +t ck +t ih , ? max ? = ? n/a ? ns ?? cke ? minimum ? high ? and ? low ? pulse ? width ? tcke ? 3 ?? 3 ?? 3 ?? 3 ?? t ck ?? average ? periodic ? refresh ? interval ? ( \ 40c ?? t c ?? +85 ? c) ? trefi ?? 7.8 ?? 7.8 ?? 7.8 ?? 7.8 ? s ? 18, ? 23 ? average ? periodic ? refresh ? interval ? (+85c ? < ? t c ?? +95 ? c) ? trefi ?? 3.9 ?? 3.9 ?? 3.9 ?? 3.9 ? s ? 18, ? 23 ? average ? periodic ? refresh ? interval ? (+95c ? < ? t c ?? +105 ? c) ? trefi ?? 3.9 ?? 3.9 ?? 3.9 ?? 3.9 ? s ? 18, ? 23 ? period ? jitter ? tjitper ?\ 125 ? 125 ?\ 125 ? 125 ?\ 100 ? 100 ?\ 100 ? 100 ? ps ? 22 ? half ? period ? jitter ? tjitdty ?\ 125 ? 125 ?\ 125 ? 125 ?\ 100 ? 100 ?\ 100 ? 100 ? ps ? 22 ? cycle ? to ? cycle ? jitter ? tjitcc ?\ 250 ? 250 ?\ 250 ? 250 ?\ 200 ? 200 ?\ 200 ? 200 ? ps ? 22 ? cumulative ? error, ? 2 ? cycles ? terr(2per) ?\ 175 ? 175 ?\ 175 ? 175 ?\ 150 ? 150 ?\ 150 ? 150 ? ps ? 22 ? cumulative ? error, ? 3 ? cycles ? terr(3per) ?\ 225 ? 225 ?\ 225 ? 225 ?\ 175 ? 175 ?\ 175 ? 175 ? ps ? 22 ? cumulative ? error, ? 4 ? cycles ? terr(4per) ?\ 250 ? 250 ?\ 250 ? 250 ?\ 200 ? 200 ?\ 200 ? 200 ? ps ? 22 ? cumulative ? error, ? 5 ? cycles ? terr(5per) ?\ 250 ? 250 ?\ 250 ? 250 ?\ 200 ? 200 ?\ 200 ? 200 ? ps ? 22 ? cumulative ? error, ? 6 \ 10 ? cycles ? terr ? (6 \ 10per) ? \ 350 ? 350 ?\ 350 ? 350 ?\ 300 ? 300 ?\ 300 ? 300 ? ps ? 22 ? cumulative ? error, ? 11 \ 50 ? cycles ? terr ? (11 \ 50per) ? \ 450 ? 450 ?\ 450 ? 450 ?\ 450 ? 450 ?\ 450 ? 450 ? ps ? 22 ? notes: ? 1. input ? slew ? rate ? is ? 1 ? v/ns ? and ? ac ? timings ? are ? guaranteed ? for ? linear ? signal ? transitions. ?? 2. the ? ck/ck# ? input ? reference ? level ? (for ? timing ? reference ? to ? ck/ck#) ? is ? the ? point ? at ? which ? ck ? and ? ck# ? cross ? the ? dqs/dqs# ? input ? reference ? level ? is ? the ? cross ? point ? when ? in ? differential ? strobe ? mode; ? the ? input ? reference ? level ? for ? signals ? other ? than ? ck/ck#, ? or ? dqs/dqs# ? is ? vref. ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 24 rev. 00d, 8/17/2010 3. inputs ? are ? not ? recognized ? as ? valid ? until ? vref ? stabilizes. ? during ? the ? period ? before ? vref ? stabilizes, ? cke ? = ? 0.2 ? x ? vddq ? is ? recognized ? as ? low. ? 4. the ? output ? timing ? reference ? voltage ? level ? is ? vtt. ? 5. the ? values ? tcl(min) ? and ? tch(min) ? refer ? to ? the ? smaller ? of ? the ? actual ? clock ? low ? time ? and ? the ? actual ? clock ? high ? time ? as ? provided ? to ? the ? device ? (i.e. ? this ? value ? can ? be ? greater ? than ? the ? minimum ? specification ? limits ? for ? tcl ? and ? tch. ? 6. for ? input ? frequency ? change ? during ? dram ? operation. ? 7. transitions ? for ? thz ? and ? tlz ? occur ? in ? the ? same ? access ? time ? windows ? as ? valid ? data ? transitions. ? these ? parameters ? are ? not ? referred ? to ? a ? specific ? voltage ? level, ? but ? specify ? when ? the ? device ? is ? no ? longer ? driving ? (hz), ? or ? begins ? driving ? (lz). ? 8. these ? parameters ? guarantee ? device ? timing, ? but ? they ? are ? not ? necessarily ? tested ? on ? each ? device. ? 9. the ? specific ? requirement ? is ? that ? dqs ? and ? dqs# ? be ? valid ? (high, ? low, ? or ? some ? point ? on ? a ? valid ? transition) ? on ? or ? before ? this ? ck ? edge. ? a ? valid ? transition ? is ? defined ? as ? monotonic ? and ? meeting ? the ? input ? slew ? rate ? specifications ? of ? the ? device. ? when ? no ? writes ? were ? previously ? in ? progress ? on ? the ? bus, ? dqs ? will ? be ? transitioning ? from ? hi \ z ? to ? logic ? low. ? if ? a ? previous ? write ? was ? in ? progress, ? dqs ? could ? be ? high, ? low, ? or ? transitioning ? from ? high ? to ? low ? at ? this ? time, ? depending ? on ? tdqss. ? when ? programmed ? in ? differential ? strobe ? mode, ? dqs ? is ? always ? the ? logic ? complement ? of ? dqs ? except ? when ? both ? are ? in ? high \ z. ? 10. the ? maximum ? limit ? for ? this ? parameter ? is ? not ? a ? device ? limit. ? the ? device ? operates ? with ? a ? greater ? value ? for ? this ? parameter, ? but ? system ? performance ? (bus ? turnaround) ? degrades ? accordingly. ? 11. a ? maximum ? of ? eight ? auto \ refresh ? commands ? can ? be ? posted ? to ? any ? given ? ddr2 ? sdram ? device. ? (note: ? trfc ? depends ? on ? dram ? density) ? 12. for ? each ? of ? the ? terms, ? if ? not ? already ? an ? integer, ? round ? to ? the ? next ? highest ? integer. ? tck ? refers ? to ? the ? application ? clock ? period. ? wr ? refers ? to ? the ? wr ? parameter ? stored ? in ? the ? mrs. ? 13. parameter ? twtr ? is ? at ? least ? two ? clocks ? independent ? of ? operation ? frequency. ? 14. user ? can ? choose ? two ? different ? active ? power \ down ? modes ? for ? additional ? power ? saving ? via ? mrs ? address ? bit ? a12. ? in ? ?standard ? active ? power \ down ? mode? ? (mrs, ? a12 ? = ? ?0?) ? a ? fast ? power \ down ? exit ? timing ? txard ? can ? be ? used. ? in ? ?low ? active ? power \ down ? mode? ? (mrs, ? a12 ? = ? ?1?) ? a ? slow ? power \ down ? exit ? timing ? txards ? has ? to ? be ? satisfied. ? 15. timings ? are ? guaranteed ? with ? command ? / ? address ? input ? slew ? rate ? of ? 1.0 ? v/ns. ? 16. timings ? are ? guaranteed ? with ? data ? / ? mask ? input ? slew ? rate ? of ? 1.0 ? v/ns. ? 17. timings ? are ? guaranteed ? with ? ck/ck# ? differential ? slew ? rate ? 2.0 ? v/ns, ? and ? dqs/dqs# ? (and ? rdqs/rdqs#) ? differential ? slew ? rate ? 2.0 ? v/ns ? in ? differential ? strobe ? mode. ? 18. if ? refresh ? timing ? or ? tds ? / ? tdh ? is ? violated, ? data ? corruption ? may ? occur ? and ? the ? data ? must ? be ? re \ written ? with ? valid ? data ? before ? a ? valid ? read ? can ? be ? executed. ? 19. in ? all ? circumstances, ? txsnr ? can ? be ? satisfied ? using ? txsnr ? = ? trfc ? + ? 10 ? ns. ? 20. the ? trcd ? timing ? parameter ? is ? valid ? for ? both ? activate ? command ? to ? read ? or ? write ? command ? with ? and ? without ? auto \ precharge. ? therefore ? a ? separate ? parameter ? trap ? for ? activate ? command ? to ? read ? or ? write ? command ? with ? auto \ precharge ? is ? not ? necessary ? anymore. ? 21. tras(max) ? is ? calculated ? from ? the ? maximum ? amount ? of ? time ? a ? ddr2 ? device ? can ? operate ? without ? a ? refresh ? command ? which ? is ? equal ? to ? 9 ? x ? trefi. ? 22. definitions: ? a. tck(avg): ? tck(avg) ? is ? calculated ? as ? the ? average ? clock ? period ? across ? any ? consecutive ? 200 ? cycle ? window. ? b. tch(avg): ? tch(avg) ? is ? defined ? as ? the ? average ? high ? pulse ? width, ? as ? calculated ? across ? any ? consecutive ? 200 ? high ? pulses. ? c. tcl(avg): ? tcl(avg) ? is ? defined ? as ? the ? average ? low ? pulse ? width, ? as ? calculated ? across ? any ? consecutive ? 200 ? low ? pulses. ? d. tjitdty: ? tjitdty ? is ? defined ? as ? the ? cumulative ? set ? of ? tch ? jitter ? and ? tcl ? jitter. ? tch ? jitter ? is ? the ? largest ? deviation ? of ? any ? single ? tch ? from ? tch(avg). ? tcl ? jitter ? is ? the ? largest ? deviation ? of ? any ? single ? tcl ? from ? tcl(avg) ? e. tjitper: ? tjitper ? is ? defined ? as ? the ? largest ? deviation ? of ? any ? single ? tck ? from ? tck(avg). ? f. tjitcc: ? tjitcc ? is ? defined ? as ? the ? difference ? in ? clock ? period ? between ? two ? consecutive ? clock ? cycles: ? tjitcc ? is ? not ? guaranteed ? through ? final ? production ? testing ? g. terr: ? terr ? is ? defined ? as ? the ? cumulative ? error ? across ? multiple ? consecutive ? cycles ? from ? tck ? (avg). ? 23. applicable ? to ? certain ? temperature ? grades. ? specified ? oper ? (tc ? and ? ta) ? must ? not ? be ? violated ? for ? each ? temperature ? grade. ? ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 25 rev. 00d, 8/17/2010 reference ? loads, ? slew ? rates ? and ? slew ? rate ? derating ? 1. ? reference ? load ? for ? timing ? measurements ? figure ? ac ? timing ? reference ? load ? represents ? the ? timing ? reference ? load ? used ? in ? defining ? the ? relevant ? timing ? parameters ? of ? the ? part. ? it ? is ? not ? intended ? to ? be ? either ? a ? precise ? representation ? of ? the ? typical ? system ? environment ? or ? a ? depiction ? of ? the ? actual ? load ? presented ? by ? a ? production ? tester. ? system ? designers ? will ? use ? ibis ? or ? other ? simulation ? tools ? to ? correlate ? the ? timing ? reference ? load ? to ? a ? system ? environment. ? manufacturers ? correlate ? to ? their ? production ? test ? conditions ? (generally ? a ? coaxial ? transmission ? line ? terminated ? at ? the ? tester ? electronics). ? this ? load ? circuit ? is ? also ? used ? for ? output ? slew ? rate ? measurements. ? ac ? timing ? reference ? load ? ck, ? ck# 25 ? timing ? reference ? points vtt=vddq/2 dq dqs dqs# rdqs rdqs# dut vddq the ? output ? timing ? reference ? voltage ? level ? for ? single ? ended ? signals ? is ? the ? crosspoint ? with ? vtt. ? the ? output ? timing ? reference ? voltage ? level ? for ? differential ? signals ? is ? the ? crosspoint ? of ? the ? true ? (e.g. ? dqs) ? and ? the ? complement ? (e.g. ? dqs#) ? signal. ? ? 2. ? slew ? rate ? measurements ?? a) ? output ? slew ? rate ?? output ? slew ? rate ? is ? characterized ? under ? the ? test ? conditions ? as ? shown ? in ? the ? figure ? below. ? ? ? output ? slew ? rate ? for ? falling ? and ? rising ? edges ? is ? measured ? between ? vtt ?\? 250 ? mv ? and ? vtt ? + ? 250 ? mv ? for ? single ? ended ? signals. ? for ? differential ? signals ? (e.g. ? dqs ? ? ? dqs#) ? output ? slew ? rate ? is ? measured ? between ? dqs ? ? ? dqs# ? = ?\? 500 ? mv ? and ? dqs ? ? ? dqs# ? = ? + ? 500 ? mv. ? output ? slew ? rate ? is ? guaranteed ? by ? design, ? but ? is ? not ? necessarily ? tested ? on ? each ? device. ? ? b) ? input ? slew ? rate ? ? input ? slew ? rate ? for ? single ? ended ? signals ? is ? measured ? from ? vref(dc) ? to ? vih(ac),min ? for ? rising ? edges ? and ? from ? vref(dc) ? to ? vil(ac),min ? for ? falling ? edges. ? for ? differential ? signals ? (e.g. ? ck ? ? ? ck#) ? slew ? rate ? for ? rising ? edges ? is ? measured ? from ? ck ? ? ? ck# ? = ?\? 250 ? mv ? to ? ck ?\? ck ? = ? + ? 500 ? mv ? (+ ? 250 ? mv ? to ?\? 500 ? mv ? for ? falling ? edges). ? test ? conditions ? are ? the ? same ? as ? for ? timing ? measurements. ? ? ? ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 26 rev. 00d, 8/17/2010 ordering ? information ? commercial ? range: ? t c ? = ? 0 ? to ? +85c; ? t a ? = ? 0c ? to ? +70c ? frequency ? speed ? grade ? cl \ t rc \ t rp ? order ? part ? no. ? organization ? package ? 333 ? mhz ? ddr2 \ 667d ? 5 \ 5 \ 5 ? is43dr81280a \ 3dbl ? 128mb ? x ? 8 ? 60 \ ball ? fbga, ? lead ? free ? ??? is43dr16640a \ 3dbl ? 64mb ? x ? 16 ? 84 \ ball ? fbga, ? lead ? free ? 400 ? mhz ? ddr2 \ 800e ? 6 \ 6 \ 6 ? is43dr81280a \ 25ebl ? 128mb ? x ? 8 ? 60 \ ball ? fbga, ? lead ? free ? ??? is43dr16640a \ 25ebl ? 64mb ? x ? 16 ? 84 \ ball ? fbga, ? lead ? free ? 400 ? mhz ? ddr2 \ 800d ? 5 \ 5 \ 5 ? is43dr16640a \ 25dbl ? 64mb ? x ? 16 ? 84 \ ball ? fbga, ? lead ? free ? ? industrial ? range: ? t c ? = ?\ 40 ? to ? +95c; ? t a ? = ?\ 40c ? to ? +85c ? frequency ? speed ? grade ? cl \ t rc \ t rp ? order ? part ? no. ? organization ? package ? 333 ? mhz ? ddr2 \ 667d ? 5 \ 5 \ 5 ? is43dr81280a \ 3dbli ? 128mb ? x ? 8 ? 60 \ ball ? fbga, ? lead ? free ? ??? is43dr16640a \ 3dbli ? 64mb ? x ? 16 ? 84 \ ball ? fbga, ? lead ? free ? ??? is43dr16640a \ 3dbi ? 64mb ? x ? 16 ? 84 \ ball ? fbga ? 400 ? mhz ? ddr2 \ 800e ? 6 \ 6 \ 6 ? is43dr81280a \ 25ebli ? 128mb ? x ? 8 ? 60 \ ball ? fbga, ? lead ? free ? ??? is43dr16640a \ 25ebli ? 64mb ? x ? 16 ? 84 \ ball ? fbga, ? lead ? free ? 400 ? mhz ? ddr2 \ 800d ? 5 \ 5 \ 5 ? is43dr81280a \ 25dbli ? 128mb ? x ? 8 ? 60 \ ball ? fbga, ? lead ? free ? ??? is43dr16640a \ 25dbli ? 64mb ? x ? 16 ? 84 \ ball ? fbga, ? lead ? free ? automotive, ? a1 ? range: ? t c ? = ?\ 40 ? to ? +95c; ? t a ? = ?\ 40c ? to ? +85c ? frequency ? speed ? grade ? cl \ t rc \ t rp ? order ? part ? no. ? organization ? package ? 333 ? mhz ? ddr2 \ 667d ? 5 \ 5 \ 5 ? is46dr81280a \ 3dbla1 ? 128mb ? x ? 8 ? 60 \ ball ? fbga, ? lead ? free ? ??? is46dr16640a \ 3dbla1 ? 64mb ? x ? 16 ? 84 \ ball ? fbga, ? lead ? free ? 400 ? mhz ? ddr2 \ 800e ? 6 \ 6 \ 6 ? is46dr81280a \ 25ebla1 ? 128mb ? x ? 8 ? 60 \ ball ? fbga, ? lead ? free ? ??? is46dr16640a \ 25ebla1 ? 64mb ? x ? 16 ? 84 \ ball ? fbga, ? lead ? free ? ? automotive, ? a2 ? range: ? t c ? = ?\ 40 ? to ? +105c; ? t a ? = ?\ 40c ? to ? +105c ? frequency ? speed ? grade ? cl \ t rc \ t rp ? order ? part ? no. ? organization ? package ? 333 ? mhz ? ddr2 \ 667d ? 5 \ 5 \ 5 ? is46dr16640a ?\ 3dbla2 ? 64mb ? x ? 16 ? 84 \ ball ? fbga, ? lead ? free ? ? ? notes: ? please ? contact ? issi ? for ? availability ? of ? leaded ? options. ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 27 rev. 00d, 8/17/2010 package outline drawing 60-ball fbga: fine pitch ball grid array outline (x8) units (mm) ?
is43/46dr81280a, ? is43/46dr16640a ? ? integrated silicon solution, inc. ? www.issi.com ? 28 rev. 00d, 8/17/2010 84-ball fbga: fine pitch ball grid array outline (x16) ?

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